at91_pwm.h

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00001 
00040 #ifndef AT91_PWM_H
00041 #define AT91_PWM_H
00042 
00046 /*\{*/
00047 #define PWM_MR_OFF              0x00000000    
00048 #define PWM_MR     (*((reg32_t *)(PWMC_BASE + PWM_MR_OFF))) 
00049 #define PWM_MR_DIVA_MASK        0x000000FF    
00050 #define PWM_MR_DIVA_SHIFT       0             
00051 #define PWM_MR_DIVB_MASK        0x00FF0000    
00052 #define PWM_MR_DIVB_SHIFT       16            
00053 
00054 #define PWM_MR_PREA_MASK        0x00000F00    
00055 #define PWM_MR_PREA_SHIFT       8             
00056 #define PWM_MR_PREB_MASK        0x0F000000    
00057 #define PWM_MR_PREB_SHIFT       24            
00058 
00059 #define PWM_MR_PRE_MCK          0             
00060 #define PWM_MR_PRE_MCK_DIV2     1             
00061 #define PWM_MR_PRE_MCK_DIV4     2             
00062 #define PWM_MR_PRE_MCK_DIV8     3             
00063 #define PWM_MR_PRE_MCK_DIV16    4             
00064 #define PWM_MR_PRE_MCK_DIV32    5             
00065 #define PWM_MR_PRE_MCK_DIV64    6             
00066 #define PWM_MR_PRE_MCK_DIV128   7             
00067 #define PWM_MR_PRE_MCK_DIV256   8             
00068 #define PWM_MR_PRE_MCK_DIV512   9             
00069 #define PWM_MR_PRE_MCK_DIV1024  10            
00070 /*\}*/
00071 
00075 /*\{*/
00076 #define PWM_CHID_MASK           0x0000000F
00077 #define PWM_CHID0               0
00078 #define PWM_CHID1               1
00079 #define PWM_CHID2               2
00080 #define PWM_CHID3               3
00081 /*\}*/
00082 
00086 /*\{*/
00087 #define PWM_ENA_OFF             0x00000004    
00088 #define PWM_ENA     (*((reg32_t *)(PWMC_BASE + PWM_ENA_OFF))) 
00089 /*\}*/
00090 
00094 /*\{*/
00095 #define PWM_DIS_OFF             0x00000008    
00096 #define PWM_DIS     (*((reg32_t *)(PWMC_BASE + PWM_DIS_OFF))) 
00097 /*\}*/
00098 
00102 /*\{*/
00103 #define PWM_SR_OFF              0x0000000C    
00104 #define PWM_SR      (*((reg32_t *)(PWMC_BASE + PWM_SR_OFF)))  
00105 /*\}*/
00106 
00110 /*\{*/
00111 #define PWM_IER_OFF             0x00000010    
00112 #define PWM_IER     (*((reg32_t *)(PWMC_BASE + PWM_IER_OFF))) 
00113 /*\}*/
00114 
00118 /*\{*/
00119 #define PWM_IDR_OFF             0x00000014    
00120 #define PWM_IDR     (*((reg32_t *)(PWMC_BASE + PWM_IDR_OFF))) 
00121 /*\}*/
00122 
00126 /*\{*/
00127 #define PWM_IMR_OFF             0x00000018    
00128 #define PWM_IMR     (*((reg32_t *)(PWMC_BASE + PWM_IMR_OFF))) 
00129 /*\}*/
00130 
00134 /*\{*/
00135 #define PWM_ISR_OFF             0x0000001C    
00136 #define PWM_ISR     (*((reg32_t *)(PWMC_BASE + PWM_ISR_OFF))) 
00137 /*\}*/
00138 
00139 #define PWM_CH0_OFF             0x00000200    
00140 #define PWM_CH1_OFF             0x00000220    
00141 #define PWM_CH2_OFF             0x00000240    
00142 #define PWM_CH3_OFF             0x00000260    
00143 
00144 
00147 /*\{*/
00148 #define PWM_CMR_OFF             0x00000000    
00149 #define PWM_CMR0    (*((reg32_t *)(PWMC_BASE + PWM_CMR_OFF + PWM_CH0_OFF))) 
00150 #define PWM_CMR1    (*((reg32_t *)(PWMC_BASE + PWM_CMR_OFF + PWM_CH1_OFF))) 
00151 #define PWM_CMR2    (*((reg32_t *)(PWMC_BASE + PWM_CMR_OFF + PWM_CH2_OFF))) 
00152 #define PWM_CMR3    (*((reg32_t *)(PWMC_BASE + PWM_CMR_OFF + PWM_CH3_OFF))) 
00153 
00154 #define PWM_CPRE_MCK_MASK       0x0000000F    
00155 #define PWM_CPRE_MCK            0             
00156 #define PWM_CPRE_MCK_DIV2       1             
00157 #define PWM_CPRE_MCK_DIV4       2             
00158 #define PWM_CPRE_MCK_DIV8       3             
00159 #define PWM_CPRE_MCK_DIV16      4             
00160 #define PWM_CPRE_MCK_DIV32      5             
00161 #define PWM_CPRE_MCK_DIV64      6             
00162 #define PWM_CPRE_MCK_DIV128     7             
00163 #define PWM_CPRE_MCK_DIV256     8             
00164 #define PWM_CPRE_MCK_DIV512     9             
00165 #define PWM_CPRE_MCK_DIV1024    10            
00166 #define PWM_CPRE_CLKA           11            
00167 #define PWM_CPRE_CLKB           12            
00168 
00169 #define PWM_CALG                8             
00170 #define PWM_CPOL                9             
00171 #define PWM_CPD                 10            
00172 /*\}*/
00173 
00174 
00178 /*\{*/
00179 #define PWM_CDTY_OFF            0x00000004    
00180 #define PWM_CDTY0   (*((reg32_t *)(PWMC_BASE + PWM_CDTY_OFF + PWM_CH0_OFF))) 
00181 #define PWM_CDTY1   (*((reg32_t *)(PWMC_BASE + PWM_CDTY_OFF + PWM_CH1_OFF))) 
00182 #define PWM_CDTY2   (*((reg32_t *)(PWMC_BASE + PWM_CDTY_OFF + PWM_CH2_OFF))) 
00183 #define PWM_CDTY3   (*((reg32_t *)(PWMC_BASE + PWM_CDTY_OFF + PWM_CH3_OFF))) 
00184 /*\}*/
00185 
00186 
00190 /*\{*/
00191 #define PWM_CPRD_OFF            0x00000008    
00192 #define PWM_CPRD0   (*((reg32_t *)(PWMC_BASE + PWM_CPRD_OFF + PWM_CH0_OFF))) 
00193 #define PWM_CPRD1   (*((reg32_t *)(PWMC_BASE + PWM_CPRD_OFF + PWM_CH1_OFF))) 
00194 #define PWM_CPRD2   (*((reg32_t *)(PWMC_BASE + PWM_CPRD_OFF + PWM_CH2_OFF))) 
00195 #define PWM_CPRD3   (*((reg32_t *)(PWMC_BASE + PWM_CPRD_OFF + PWM_CH3_OFF))) 
00196 /*\}*/
00197 
00198 
00202 /*\{*/
00203 #define PWM_CCNT_OFF            0x0000000C    
00204 #define PWM_CCNT0   (*((reg32_t *)(PWMC_BASE + PWM_CCNT_OFF + PWM_CH0_OFF))) 
00205 #define PWM_CCNT1   (*((reg32_t *)(PWMC_BASE + PWM_CCNT_OFF + PWM_CH1_OFF))) 
00206 #define PWM_CCNT2   (*((reg32_t *)(PWMC_BASE + PWM_CCNT_OFF + PWM_CH2_OFF))) 
00207 #define PWM_CCNT3   (*((reg32_t *)(PWMC_BASE + PWM_CCNT_OFF + PWM_CH3_OFF))) 
00208 /*\}*/
00209 
00210 
00214 /*\{*/
00215 #define PWM_CUPD_OFF            0x00000010    
00216 #define PWM_CUPD0   (*((reg32_t *)(PWMC_BASE + PWM_CUPD_OFF + PWM_CH0_OFF))) 
00217 #define PWM_CUPD1   (*((reg32_t *)(PWMC_BASE + PWM_CUPD_OFF + PWM_CH1_OFF))) 
00218 #define PWM_CUPD2   (*((reg32_t *)(PWMC_BASE + PWM_CUPD_OFF + PWM_CH2_OFF))) 
00219 #define PWM_CUPD3   (*((reg32_t *)(PWMC_BASE + PWM_CUPD_OFF + PWM_CH3_OFF))) 
00220 /*\}*/
00221 
00222 #endif /* AT91_PWM_H */