at91_spi.h

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00001 
00042 /*
00043  * Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
00044  *
00045  * Redistribution and use in source and binary forms, with or without
00046  * modification, are permitted provided that the following conditions
00047  * are met:
00048  *
00049  * 1. Redistributions of source code must retain the above copyright
00050  *    notice, this list of conditions and the following disclaimer.
00051  * 2. Redistributions in binary form must reproduce the above copyright
00052  *    notice, this list of conditions and the following disclaimer in the
00053  *    documentation and/or other materials provided with the distribution.
00054  * 3. Neither the name of the copyright holders nor the names of
00055  *    contributors may be used to endorse or promote products derived
00056  *    from this software without specific prior written permission.
00057  *
00058  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00059  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00060  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00061  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00062  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00063  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00064  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00065  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00066  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00067  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00068  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00069  * SUCH DAMAGE.
00070  *
00071  * For additional information see http://www.ethernut.de/
00072 
00073  */
00074 
00075 #ifndef AT91_SPI_H
00076 #define AT91_SPI_H
00077 
00081 /*\{*/
00082 #define SPI_CR_OFF      0x00000000  
00083 
00084 #define SPI_SPIEN                0  
00085 #define SPI_SPIDIS               1  
00086 #define SPI_SWRST                7  
00087 #define SPI_LASTXFER            24  
00088 /*\}*/
00089 
00093 /*\{*/
00094 #define SPI_MR_OFF      0x00000004  
00095 
00096 #define SPI_MSTR                 0  
00097 #define SPI_PS                   1  
00098 #define SPI_PCSDEC               2 
00099 #define SPI_FDIV                 3  
00100 #define SPI_MODFDIS              4  
00101 #define SPI_LLB                  7  
00102 #define SPI_PCS         0x000F0000  
00103 #define SPI_PCS_0       0x000E0000  
00104 #define SPI_PCS_1       0x000D0000  
00105 #define SPI_PCS_2       0x000B0000  
00106 #define SPI_PCS_3       0x00070000  
00107 #define SPI_PCS_SHIFT           16  
00108 #define SPI_DLYBCS      0xFF000000  
00109 #define SPI_DLYBCS_SHIFT        24  
00110 /*\}*/
00111 
00115 /*\{*/
00116 #define SPI_RDR_OFF     0x00000008  
00117 
00118 #define SPI_RD          0x0000FFFF  
00119 #define SPI_RD_SHIFT             0  
00120 /*\}*/
00121 
00125 /*\{*/
00126 #define SPI_TDR_OFF     0x0000000C  
00127 
00128 #define SPI_TD          0x0000FFFF  
00129 #define SPI_TD_SHIFT             0  
00130 /*\}*/
00131 
00135 /*\{*/
00136 #define SPI_SR_OFF      0x00000010  
00137 #define SPI_IER_OFF     0x00000014  
00138 #define SPI_IDR_OFF     0x00000018  
00139 #define SPI_IMR_OFF     0x0000001C  
00140 
00141 #define SPI_RDRF                 0  
00142 #define SPI_TDRE                 1  
00143 #define SPI_MODF                 2  
00144 #define SPI_OVRES                3  
00145 #define SPI_ENDRX                4  
00146 #define SPI_ENDTX                5  
00147 #define SPI_RXBUFF               6  
00148 #define SPI_TXBUFE               7  
00149 #define SPI_NSSR                 8  
00150 #define SPI_TXEMPTY              9  
00151 #define SPI_SPIENS              16  
00152 /*\}*/
00153 
00157 /*\{*/
00158 #define SPI_CSR0_OFF    0x00000030  
00159 #define SPI_CSR1_OFF    0x00000034  
00160 #define SPI_CSR2_OFF    0x00000038  
00161 #define SPI_CSR3_OFF    0x0000003C  
00162 
00163 #define SPI_CPOL                 0  
00164 #define SPI_NCPHA                1  
00165 #define SPI_CSAAT                3  
00166 #define SPI_BITS        0x000000F0  
00167 #define SPI_BITS_8      0x00000000  
00168 #define SPI_BITS_9      0x00000010  
00169 #define SPI_BITS_10     0x00000020  
00170 #define SPI_BITS_11     0x00000030  
00171 #define SPI_BITS_12     0x00000040  
00172 #define SPI_BITS_13     0x00000050  
00173 #define SPI_BITS_14     0x00000060  
00174 #define SPI_BITS_15     0x00000070  
00175 #define SPI_BITS_16     0x00000080  
00176 #define SPI_BITS_SHIFT           4  
00177 #define SPI_SCBR        0x0000FF00  
00178 #define SPI_SCBR_SHIFT           8  
00179 #define SPI_DLYBS       0x00FF0000  
00180 #define SPI_DLYBS_SHIFT         16  
00181 #define SPI_DLYBCT      0xFF000000  
00182 #define SPI_DLYBCT_SHIFT        24  
00183 /*\}*/
00184 
00188 /*\{*/
00189 #if defined(SPI_BASE)
00190     #define SPI0_BASE   SPI_BASE
00191     #define SPI_CR      SPI0_CR     
00192     #define SPI_MR      SPI0_MR     
00193     #define SPI_RDR     SPI0_RDR    
00194     #define SPI_TDR     SPI0_TDR    
00195     #define SPI_SR      SPI0_SR     
00196     #define SPI_IER     SPI0_IER    
00197     #define SPI_IDR     SPI0_IDR    
00198     #define SPI_IMR     SPI0_IMR    
00199     #define SPI_CSR0    SPI0_CSR0   
00200     #define SPI_CSR1    SPI0_CSR1   
00201     #define SPI_CSR2    SPI0_CSR2   
00202     #define SPI_CSR3    SPI0_CSR3   
00203     #if defined(SPI_HAS_PDC)
00204         #define SPI_RPR     SPI0_RPR    
00205         #define SPI_RCR     SPI0_RCR    
00206         #define SPI_TPR     SPI0_TPR    
00207         #define SPI_TCR     SPI0_TCR    
00208         #define SPI_RNPR    SPI0_RNPR   
00209         #define SPI_RNCR    SPI0_RNCR   
00210         #define SPI_TNPR    SPI0_TNPR   
00211         #define SPI_TNCR    SPI0_TNCR   
00212         #define SPI_PTCR    SPI0_PTCR   
00213         #define SPI_PTSR    SPI0_PTSR   
00214     #endif /* SPI_HAS_PDC */
00215 #endif /* SPI_BASE */
00216 /*\}*/
00217 
00221 /*\{*/
00222 #if defined(SPI0_BASE)
00223     #define SPI0_CR     (*((reg32_t *)(SPI0_BASE + SPI_CR_OFF)))        
00224     #define SPI0_MR     (*((reg32_t *)(SPI0_BASE + SPI_MR_OFF)))        
00225     #define SPI0_RDR    (*((reg32_t *)(SPI0_BASE + SPI_RDR_OFF)))       
00226     #define SPI0_TDR    (*((reg32_t *)(SPI0_BASE + SPI_TDR_OFF)))       
00227     #define SPI0_SR     (*((reg32_t *)(SPI0_BASE + SPI_SR_OFF)))        
00228     #define SPI0_IER    (*((reg32_t *)(SPI0_BASE + SPI_IER_OFF)))       
00229     #define SPI0_IDR    (*((reg32_t *)(SPI0_BASE + SPI_IDR_OFF)))       
00230     #define SPI0_IMR    (*((reg32_t *)(SPI0_BASE + SPI_IMR_OFF)))       
00231     #define SPI0_CSR0   (*((reg32_t *)(SPI0_BASE + SPI_CSR0_OFF)))      
00232     #define SPI0_CSR1   (*((reg32_t *)(SPI0_BASE + SPI_CSR1_OFF)))      
00233     #define SPI0_CSR2   (*((reg32_t *)(SPI0_BASE + SPI_CSR2_OFF)))      
00234     #define SPI0_CSR3   (*((reg32_t *)(SPI0_BASE + SPI_CSR3_OFF)))      
00235     #if defined(SPI_HAS_PDC)
00236         #define SPI0_RPR    (*((reg32_t *)(SPI0_BASE + PERIPH_RPR_OFF))    
00237         #define SPI0_RCR    (*((reg32_t *)(SPI0_BASE + PERIPH_RCR_OFF))    
00238         #define SPI0_TPR    (*((reg32_t *)(SPI0_BASE + PERIPH_TPR_OFF))    
00239         #define SPI0_TCR    (*((reg32_t *)(SPI0_BASE + PERIPH_TCR_OFF))    
00240         #define SPI0_RNPR   (*((reg32_t *)(SPI0_BASE + PERIPH_RNPR_OFF))   
00241         #define SPI0_RNCR   (*((reg32_t *)(SPI0_BASE + PERIPH_RNCR_OFF))   
00242         #define SPI0_TNPR   (*((reg32_t *)(SPI0_BASE + PERIPH_TNPR_OFF))   
00243         #define SPI0_TNCR   (*((reg32_t *)(SPI0_BASE + PERIPH_TNCR_OFF))   
00244         #define SPI0_PTCR   (*((reg32_t *)(SPI0_BASE + PERIPH_PTCR_OFF))   
00245         #define SPI0_PTSR   (*((reg32_t *)(SPI0_BASE + PERIPH_PTSR_OFF))   
00246     #endif /* SPI_HAS_PDC */
00247 #endif /* SPI0_BASE */
00248 /*\}*/
00249 
00253 /*\{*/
00254 #if defined(SPI1_BASE)
00255     #define SPI1_CR     (*((reg32_t *)(SPI1_BASE + SPI_CR_OFF)))        
00256     #define SPI1_MR     (*((reg32_t *)(SPI1_BASE + SPI_MR_OFF)))        
00257     #define SPI1_RDR    (*((reg32_t *)(SPI1_BASE + SPI_RDR_OFF)))       
00258     #define SPI1_TDR    (*((reg32_t *)(SPI1_BASE + SPI_TDR_OFF)))       
00259     #define SPI1_SR     (*((reg32_t *)(SPI1_BASE + SPI_SR_OFF)))        
00260     #define SPI1_IER    (*((reg32_t *)(SPI1_BASE + SPI_IER_OFF)))       
00261     #define SPI1_IDR    (*((reg32_t *)(SPI1_BASE + SPI_IDR_OFF)))       
00262     #define SPI1_IMR    (*((reg32_t *)(SPI1_BASE + SPI_IMR_OFF)))       
00263     #define SPI1_CSR0   (*((reg32_t *)(SPI1_BASE + SPI_CSR0_OFF)))      
00264     #define SPI1_CSR1   (*((reg32_t *)(SPI1_BASE + SPI_CSR1_OFF)))      
00265     #define SPI1_CSR2   (*((reg32_t *)(SPI1_BASE + SPI_CSR2_OFF)))      
00266     #define SPI1_CSR3   (*((reg32_t *)(SPI1_BASE + SPI_CSR3_OFF)))      
00267     #if defined(SPI_HAS_PDC)
00268         #define SPI1_RPR    (*((reg32_t *)(SPI1_BASE + PERIPH_RPR_OFF)))    
00269         #define SPI1_RCR    (*((reg32_t *)(SPI1_BASE + PERIPH_RCR_OFF)))    
00270         #define SPI1_TPR    (*((reg32_t *)(SPI1_BASE + PERIPH_TPR_OFF)))    
00271         #define SPI1_TCR    (*((reg32_t *)(SPI1_BASE + PERIPH_TCR_OFF)))    
00272         #define SPI1_RNPR   (*((reg32_t *)(SPI1_BASE + PERIPH_RNPR_OFF)))   
00273         #define SPI1_RNCR   (*((reg32_t *)(SPI1_BASE + PERIPH_RNCR_OFF)))   
00274         #define SPI1_TNPR   (*((reg32_t *)(SPI1_BASE + PERIPH_TNPR_OFF)))   
00275         #define SPI1_TNCR   (*((reg32_t *)(SPI1_BASE + PERIPH_TNCR_OFF)))   
00276         #define SPI1_PTCR   (*((reg32_t *)(SPI1_BASE + PERIPH_PTCR_OFF)))   
00277         #define SPI1_PTSR   (*((reg32_t *)(SPI1_BASE + PERIPH_PTSR_OFF)))   
00278     #endif /* SPI_HAS_PDC */
00279 #endif /* SPI1_BASE */
00280 /*\}*/
00281 
00282 #endif  /* AT91_SPI_H */