at91_us.h

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/*
 * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the copyright holders nor the names of
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * For additional information see http://www.ethernut.de/
 */

#ifndef AT91_US_H
#define AT91_US_H

/*\{*/
#define US_CR_OFF               0x00000000      
#define US0_CR  (*((reg32_t *)(USART0_BASE + US_CR_OFF)))       
#define US1_CR  (*((reg32_t *)(USART1_BASE + US_CR_OFF)))       
#define US_RSTRX                         2      
#define US_RSTTX                         3      
#define US_RXEN                          4      
#define US_RXDIS                         5      
#define US_TXEN                          6      
#define US_TXDIS                         7      
#define US_RSTSTA                        8      
#define US_STTBRK                        9      
#define US_STPBRK                        10     
#define US_STTTO                         11     
#define US_SENDA                         12     
#define US_RSTIT                         13     
#define US_RSTNAK                        14     
#define US_RETTO                         15     
#define US_DTREN                         16     
#define US_DTRDIS                        17     
#define US_RTSEN                         18     
#define US_RTSDIS                        19     
/*\}*/

/*\{*/
#define US_MR_OFF               0x00000004      
#define US0_MR  (*((reg32_t *)(USART0_BASE + US_MR_OFF)))       
#define US1_MR  (*((reg32_t *)(USART1_BASE + US_MR_OFF)))       

#define US_USART_MODE_MASK      0x0000000F      
#define US_USART_MODE_NORMA     0x00000000      
#define US_USART_MODE_RS485     0x00000001      
#define US_USART_MODE_HW_HDSH   0x00000002      
#define US_USART_MODE_MODEM     0x00000003      
#define US_USART_MODE_ISO7816T0 0x00000004      
#define US_USART_MODE_ISO7816T1 0x00000006      
#define US_USART_MODE_IRDA      0x00000008      

#define US_CLKS_MASK            0x00000030      
#define US_CLKS_MCK             0x00000000      
#define US_CLKS_MCK8            0x00000010      
#define US_CLKS_SCK             0x00000020      
#define US_CLKS_SLCK            0x00000030      

#define US_CHRL_MASK            0x000000C0      
#define US_CHRL_5               0x00000000      
#define US_CHRL_6               0x00000040      
#define US_CHRL_7               0x00000080      
#define US_CHRL_8               0x000000C0      

#define US_SYNC                          8      

#define US_PAR_MASK             0x00000E00      
#define US_PAR_EVEN             0x00000000      
#define US_PAR_ODD              0x00000200      
#define US_PAR_SPACE            0x00000400      
#define US_PAR_MARK             0x00000600      
#define US_PAR_NO               0x00000800      
#define US_PAR_MULTIDROP        0x00000C00      

#define US_NBSTOP_MASK          0x00003000      
#define US_NBSTOP_1             0x00000000      
#define US_NBSTOP_1_5           0x00001000      
#define US_NBSTOP_2             0x00002000      

#define US_CHMODE_MASK              0x0000C000  
#define US_CHMODE_NORMAL            0x00000000  
#define US_CHMODE_AUTOMATIC_ECHO    0x00004000  
#define US_CHMODE_LOCAL_LOOPBACK    0x00008000  
#define US_CHMODE_REMOTE_LOOPBACK   0x0000C000  

#define US_MSBF                         16      
#define US_MODE9                        17      
#define US_CLKO                         18      
#define US_OVER                         19      
#define US_INACK                        20      
#define US_DSNACK                       21      

#define US_MAX_INTERATION_MASK      0x07000000  

#define US_FILTER                       28      

/*\}*/

/*\{*/
#define US_IER_OFF              0x00000008      
#define US0_IER (*((reg32_t *)(USART0_BASE + US_IER_OFF)))      
#define US1_IER (*((reg32_t *)(USART1_BASE + US_IER_OFF)))      

#define US_IDR_OFF              0x0000000C      
#define US0_IDR (*((reg32_t *)(USART0_BASE + US_IDR_OFF)))      
#define US1_IDR (*((reg32_t *)(USART1_BASE + US_IDR_OFF)))      

#define US_IMR_OFF              0x00000010      
#define US0_IMR (*((reg32_t *)(USART0_BASE + US_IMR_OFF)))      
#define US1_IMR (*((reg32_t *)(USART1_BASE + US_IMR_OFF)))      

#define US_CSR_OFF              0x00000014      
#define US0_CSR (*((reg32_t *)(USART0_BASE + US_CSR_OFF)))      
#define US1_CSR (*((reg32_t *)(USART1_BASE + US_CSR_OFF)))      
#define US_CSR_RI                       20      
#define US_CSR_DSR                      21      
#define US_CSR_DCD                      22      
#define US_CSR_CTS                      23      

#define US_RXRDY                         0      
#define US_TXRDY                         1      
#define US_RXBRK                         2      
#define US_ENDRX                         3      
#define US_ENDTX                         4      
#define US_OVRE                          5      
#define US_FRAME                         6      
#define US_PARE                          7      
#define US_TIMEOUT                       8      
#define US_TXEMPTY                       9      
#define US_ITERATION                    10      
#define US_TXBUFE                       11      
#define US_RXBUFF                       12      
#define US_NACK                         13      
#define US_RIIC                         16      
#define US_DSRIC                        17      
#define US_DCDIC                        18      
#define US_CTSIC                        19      


/*\{*/
#define US_RHR_OFF              0x00000018      
#define US0_RHR (*((reg32_t *)(USART0_BASE + US_RHR_OFF)))      
#define US1_RHR (*((reg32_t *)(USART1_BASE + US_RHR_OFF)))      
#define US_RHR_RXCHR_MASK       0x000001FF      
#define US_RHR_RXSYNH                   15      
/*\}*/

/*\{*/
#define US_THR_OFF              0x0000001C      
#define US0_THR (*((reg32_t *)(USART0_BASE + US_THR_OFF)))      
#define US1_THR (*((reg32_t *)(USART1_BASE + US_THR_OFF)))      
#define US_THR_TXCHR_MASK       0x000001FF      
#define US_THR_TXSYNH                   15      
/*\}*/

/*\{*/
#define US_BRGR_OFF             0x00000020      
#define US0_BRGR (*((reg32_t *)(USART0_BASE + US_BRGR_OFF)))    
#define US1_BRGR (*((reg32_t *)(USART1_BASE + US_BRGR_OFF)))    
/*\}*/

/*\{*/
#define US_RTOR_OFF             0x00000024      
#define US0_RTOR (*((reg32_t *)(USART0_BASE + US_RTOR_OFF)))    
#define US1_RTOR (*((reg32_t *)(USART1_BASE + US_RTOR_OFF)))    
/*\}*/

/*\{*/
#define US_TTGR_OFF             0x00000028      
#define US0_TTGR (*((reg32_t *)(USART0_BASE + US_TTGR_OFF)))    
#define US1_TTGR (*((reg32_t *)(USART1_BASE + US_TTGR_OFF)))    
/*\}*/

/*\{*/
#define US_FIDI_OFF             0x00000040      
#define US0_FIDI (*((reg32_t *)(USART0_BASE + US_FIDI_OFF)))    
#define US1_FIDI (*((reg32_t *)(USART1_BASE + US_FIDI_OFF)))    
/*\}*/

/*\{*/
#define US_NER_OFF              0x00000044      
#define US0_NER  (*((reg32_t *)(USART0_BASE + US_NER_OFF)))     
#define US1_NER  (*((reg32_t *)(USART1_BASE + US_NER_OFF)))     
/*\}*/

/*\{*/
#define US_IF_OFF               0x0000004C      
#define US0_IF (*((reg32_t *)(USART0_BASE + US_IF_OFF)))        
#define US1_IF (*((reg32_t *)(USART1_BASE + US_IF_OFF)))        
/*\}*/

#if USART_HAS_PDC

    /*\{*/
    #define US0_RPR (*((reg32_t *)(USART0_BASE + PERIPH_RPR_OFF)))      
    #define US1_RPR (*((reg32_t *)(USART1_BASE + PERIPH_RPR_OFF)))      
    /*\}*/

    /*\{*/
    #define US0_RCR (*((reg32_t *)(USART0_BASE + PERIPH_RCR_OFF)))      
    #define US1_RCR (*((reg32_t *)(USART1_BASE + PERIPH_RCR_OFF)))      
    /*\}*/

    /*\{*/
    #define US0_TPR (*((reg32_t *)(USART0_BASE + PERIPH_TPR_OFF)))      
    #define US1_TPR (*((reg32_t *)(USART1_BASE + PERIPH_TPR_OFF)))      
    /*\}*/

    /*\{*/
    #define US0_TCR (*((reg32_t *)(USART0_BASE + PERIPH_TCR_OFF)))      
    #define US1_TCR (*((reg32_t *)(USART1_BASE + PERIPH_TCR_OFF)))      
    /*\}*/

    #if defined(PERIPH_RNPR_OFF) && defined(PERIPH_RNCR_OFF)
    #define US0_RNPR   (*((reg32_t *)(USART0_BASE + PERIPH_RNPR_OFF)))  
    #define US1_RNPR   (*((reg32_t *)(USART1_BASE + PERIPH_RNPR_OFF)))  
    #define US0_RNCR   (*((reg32_t *)(USART0_BASE + PERIPH_RNCR_OFF)))  
    #define US1_RNCR   (*((reg32_t *)(USART1_BASE + PERIPH_RNCR_OFF)))  
    #endif

    #if defined(PERIPH_TNPR_OFF) && defined(PERIPH_TNCR_OFF)
    #define US0_TNPR   (*((reg32_t *)(USART0_BASE + PERIPH_TNPR_OFF)))  
    #define US1_TNPR   (*((reg32_t *)(USART1_BASE + PERIPH_TNPR_OFF)))  
    #define US0_TNCR   (*((reg32_t *)(USART0_BASE + PERIPH_TNCR_OFF)))  
    #define US1_TNCR   (*((reg32_t *)(USART1_BASE + PERIPH_TNCR_OFF)))  
    #endif

    #if defined(PERIPH_PTCR_OFF)
    #define US0_PTCR   (*((reg32_t *)(USART0_BASE + PERIPH_PTCR_OFF)))  
    #define US1_PTCR   (*((reg32_t *)(USART1_BASE + PERIPH_PTCR_OFF)))  
    #endif

    #if defined(PERIPH_PTSR_OFF)
    #define US0_PTSR   (*((reg32_t *)(USART0_BASE + PERIPH_PTSR_OFF)))  
    #define US1_PTSR   (*((reg32_t *)(USART1_BASE + PERIPH_PTSR_OFF)))  
    #endif

#endif  /* USART_HAS_PDC */

#endif /* AT91_US_H */