pwm_at91.c

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#include "pwm_at91.h"

#include <hw/hw_cpu.h>

#include <cfg/macros.h>
#include <cfg/debug.h>
#include <io/arm.h>

#include "appconfig.h"

static PwmChannel pwm_map[PWM_CNT] =
{
    {//PWM Channel 0
        .duty_zero = false,
        .pwm_pin = BV(PWM0),
        .mode_reg = &PWM_CMR0,
        .duty_reg = &PWM_CDTY0,
        .period_reg = &PWM_CPRD0,
        .update_reg = &PWM_CUPD0,
    },
    {//PWM Channel 1
        .duty_zero = false,
        .pwm_pin = BV(PWM1),
        .mode_reg = &PWM_CMR1,
        .duty_reg = &PWM_CDTY1,
        .period_reg = &PWM_CPRD1,
        .update_reg = &PWM_CUPD1,
    },
    {//PWM Channel 2
        .duty_zero = false,
        .pwm_pin = BV(PWM2),
        .mode_reg = &PWM_CMR2,
        .duty_reg = &PWM_CDTY2,
        .period_reg = &PWM_CPRD2,
        .update_reg = &PWM_CUPD2,
    },
    {//PWM Channel 3
        .duty_zero = false,
        .pwm_pin = BV(PWM3),
        .mode_reg = &PWM_CMR3,
        .duty_reg = &PWM_CDTY3,
        .period_reg = &PWM_CPRD3,
        .update_reg = &PWM_CUPD3,
    }
};


pwm_period_t pwm_hw_getPeriod(PwmDev dev)
{
    return *pwm_map[dev].period_reg;
}

void pwm_hw_setFrequency(PwmDev dev, uint32_t freq)
{
    uint32_t period = 0;

    for(int i = 0; i <= PWM_HW_MAX_PRESCALER_STEP; i++)
    {
        period = CLOCK_FREQ / (BV(i) * freq);
//      TRACEMSG("period[%d], prescale[%d]", period, i);
        if ((period < PWM_HW_MAX_PERIOD) && (period != 0))
        {
            //Clean previous channel prescaler, and set new
            *pwm_map[dev].mode_reg &= ~PWM_CPRE_MCK_MASK;
            *pwm_map[dev].mode_reg |= i;
            //Set pwm period
            *pwm_map[dev].period_reg = period;
            break;
        }
    }

    PWM_ENA = BV(dev);

//  TRACEMSG("PWM ch[%d] period[%d]", dev, period);
}

void pwm_hw_setDutyUnlock(PwmDev dev, uint16_t duty)
{
    ASSERT(duty <= (uint16_t)*pwm_map[dev].period_reg);


    /*
     * WARNING: is forbidden to write 0 to duty cycle value,
     * and so for duty = 0 we must enable PIO and clear output!
     */
    if (!duty)
    {
        PWM_PIO_PER = pwm_map[dev].pwm_pin;
        pwm_map[dev].duty_zero = true;
    }
    else
    {
        ASSERT(PWM_CCNT0);
        PWM_PIO_PDR = pwm_map[dev].pwm_pin;
        *pwm_map[dev].update_reg = duty;
        pwm_map[dev].duty_zero = false;
    }

//  TRACEMSG("PWM ch[%d] duty[%d], period[%ld]", dev, duty, *pwm_map[dev].period_reg);
}


void pwm_hw_enable(PwmDev dev)
{
    if (!pwm_map[dev].duty_zero)
        PWM_PIO_PDR = pwm_map[dev].pwm_pin;
}

void pwm_hw_disable(PwmDev dev)
{
    PWM_PIO_PER = pwm_map[dev].pwm_pin;
}


void pwm_hw_init(void)
{

    /*
     * Init pwm:
     * WARNING: is forbidden to write 0 to duty cycle value,
     * and so for duty = 0 we must enable PIO and clear output!
     * - clear PIO outputs
     * - enable PIO outputs
     * - Disable PIO and enable PWM functions
     * - Power on PWM
     */
    PWM_PIO_CODR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
    PWM_PIO_OER = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
    PWM_PIO_PDR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
    PWM_PIO_ABSR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
    PMC_PCER |= BV(PWMC_ID);

    /* Disable all channels. */
    PWM_DIS = 0xFFFFFFFF;
    /* Disable prescalers A and B */
    PWM_MR = 0;

    /*
     * Set pwm mode:
     * - set period alidned to left
     * - set output waveform to low level
     * - allow duty cycle modify at next period event
     */
    for (int ch = 0; ch < PWM_CNT; ch++)
        *pwm_map[ch].mode_reg = 0;
}