adc_at91.c

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#include "adc_at91.h"

#include <cpu/irq.h>

#include "cfg/cfg_adc.h"
#include "cfg/cfg_kern.h"
#include <cfg/macros.h>
#include <cfg/compiler.h>

// Define log settings for cfg/log.h.
#define LOG_LEVEL         ADC_LOG_LEVEL
#define LOG_FORMAT        ADC_LOG_FORMAT
#include <cfg/log.h>

#include <drv/adc.h>

#include <io/arm.h>

#if CONFIG_KERN
    #include <cfg/module.h>
    #include <kern/proc.h>
    #include <kern/signal.h>


    #if !CONFIG_KERN_SIGNALS
        #error Signals must be active to use ADC with kernel
    #endif

    /* Signal adc convertion end */
    #define SIG_ADC_COMPLETE SIG_USER0

    /* ADC waiting process */
    static struct Process *adc_process;

    static void ISR_FUNC adc_conversion_end_irq(void)
    {
        sig_signal(adc_process, SIG_ADC_COMPLETE);

        /* Inform hw that we have served the IRQ */
        AIC_EOICR = 0;
    }

    static void adc_enable_irq(void)
    {

        // Disable all interrupt
        ADC_IDR = 0xFFFFFFFF;

        //Register interrupt vector
        AIC_SVR(ADC_ID) = adc_conversion_end_irq;
        AIC_SMR(ADC_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED;
        AIC_IECR = BV(ADC_ID);

        //Enable data ready irq
        ADC_IER = BV(ADC_DRDY);
    }

#endif /* CONFIG_KERN */


INLINE void adc_hw_select_ch(uint8_t ch)
{
    //Disable all channels
    ADC_CHDR = ADC_CH_MASK;
    //Enable select channel
    ADC_CHER = BV(ch);
}


INLINE uint16_t adc_hw_read(void)
{
    ASSERT(!(ADC_SR & ADC_EOC_MASK));

    #if CONFIG_KERN
        adc_process = proc_current();
    #endif

    // Start convertion
    ADC_CR = BV(ADC_START);

    #if CONFIG_KERN
        // Ensure IRQs enabled.
        IRQ_ASSERT_ENABLED();
        sig_wait(SIG_ADC_COMPLETE);
    #else
        //Wait in polling until is done
        while (!(ADC_SR & BV(ADC_DRDY)));
    #endif

    //Return the last converted data
    return(ADC_LCDR);
}

INLINE void adc_hw_init(void)
{
    //Init ADC pins.
    ADC_INIT_PINS();

    /*
     * Set adc mode register:
     * - Disable hardware trigger and enable software trigger.
     * - Select normal mode.
     * - Set ADC_BITS bit convertion resolution.
     *
     * \{
     */
    ADC_MR = 0;
    #if ADC_BITS == 10
        ADC_MR &= ~BV(ADC_LOWRES);
    #elif ADC_BITS == 8
        ADC_MR |= BV(ADC_LOWRES);
    #else
        #error No select bit resolution is supported to this CPU
    #endif
    /* \} */

    LOG_INFO("prescaler[%ld], stup[%ld], shtim[%ld]\n",ADC_COMPUTED_PRESCALER, ADC_COMPUTED_STARTUPTIME,  ADC_COMPUTED_SHTIME);


    //Apply computed prescaler value
    ADC_MR &= ~ADC_PRESCALER_MASK;
    ADC_MR |= ((ADC_COMPUTED_PRESCALER << ADC_PRESCALER_SHIFT) & ADC_PRESCALER_MASK);
    LOG_INFO("prescaler[%ld]\n", (ADC_COMPUTED_PRESCALER << ADC_PRESCALER_SHIFT) & ADC_PRESCALER_MASK);

    //Apply computed start up time
    ADC_MR &= ~ADC_STARTUP_MASK;
    ADC_MR |= ((ADC_COMPUTED_STARTUPTIME << ADC_STARTUP_SHIFT) & ADC_STARTUP_MASK);
    LOG_INFO("sttime[%ld]\n", (ADC_COMPUTED_STARTUPTIME << ADC_STARTUP_SHIFT) & ADC_STARTUP_MASK);

    //Apply computed sample and hold time
    ADC_MR &= ~ADC_SHTIME_MASK;
    ADC_MR |= ((ADC_COMPUTED_SHTIME << ADC_SHTIME_SHIFT) & ADC_SHTIME_MASK);
    LOG_INFO("shtime[%ld]\n", (ADC_COMPUTED_SHTIME << ADC_SHTIME_SHIFT) & ADC_SHTIME_MASK);

    #if CONFIG_KERN
        //Register and enable irq for adc.
        adc_enable_irq();
    #endif

}