at91_adc.h

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00001 
00042 #ifndef AT91_ADC_H
00043 #define AT91_ADC_H
00044 
00045 
00049 #define ADC_CR_OFF              0x00000000     
00050 #define ADC_CR          (*((reg32_t *)(ADC_BASE + ADC_CR_OFF))) 
00051 #define ADC_SWRST                        0      
00052 #define ADC_START                        1      
00053 
00054 
00058 #define ADC_MR_OFF              0x00000004     
00059 #define ADC_MR          (*((reg32_t *)(ADC_BASE + ADC_MR_OFF))) 
00060 #define ADC_TRGEN                        0     
00061 
00062 #define ADC_TRGSEL_TIOA0         0x00000000    
00063 #define ADC_TRGSEL_TIOA1         0x00000002    
00064 #define ADC_TRGSEL_TIOA2         0x00000004    
00065 #define ADC_TRGSEL_EXT           0x0000000C    
00066 
00067 #define ADC_LOWRES                        4   
00068 #define ADC_SLEEP                         5   
00069 
00070 
00074 #define ADC_PRESCALER_MASK       0x00003F00   
00075 #define ADC_PRESCALER_SHIFT               8   
00076 
00077 
00081 #define ADC_STARTUP_MASK         0x001F0000   
00082 #define ADC_STARTUP_SHIFT                16   
00083 
00084 
00089 #define ADC_SHTIME_MASK          0x0F000000   
00090 #define ADC_SHTIME_SHIFT                 24   
00091 
00092 
00096 #define ADC_CHER_OFF             0x00000010     
00097 #define ADC_CHER          (*((reg32_t *)(ADC_BASE + ADC_CHER_OFF))) 
00098 
00099 
00102 #define ADC_CHDR_OFF             0x00000014     
00103 #define ADC_CHDR          (*((reg32_t *)(ADC_BASE + ADC_CHDR_OFF))) 
00104 
00105 
00108 #define ADC_CHSR_OFF             0x00000018     
00109 #define ADC_CHSR          (*((reg32_t *)(ADC_BASE + ADC_CHSR_OFF))) 
00110 
00111 #define ADC_CH_MASK              0x000000FF    
00112 #define ADC_CH0                           0    
00113 #define ADC_CH1                           1    
00114 #define ADC_CH2                           2    
00115 #define ADC_CH3                           3    
00116 #define ADC_CH4                           4    
00117 #define ADC_CH5                           5    
00118 #define ADC_CH6                           6    
00119 #define ADC_CH7                           7    
00120 
00121 
00124 #define ADC_SR_OFF               0x0000001C     
00125 #define ADC_SR          (*((reg32_t *)(ADC_BASE + ADC_SR_OFF))) 
00126 
00127 
00130 #define ADC_IER_OFF              0x00000024     
00131 #define ADC_IER          (*((reg32_t *)(ADC_BASE + ADC_IER_OFF))) 
00132 
00133 
00136 #define ADC_IDR_OFF              0x00000028     
00137 #define ADC_IDR          (*((reg32_t *)(ADC_BASE + ADC_IDR_OFF))) 
00138 
00139 
00142 #define ADC_IMR_OFF              0x0000002C     
00143 #define ADC_IMR          (*((reg32_t *)(ADC_BASE + ADC_IMR_OFF))) 
00144 
00145 #define ADC_EOC_MASK             0x000000FF    
00146 #define ADC_EOC0                          0    
00147 #define ADC_EOC1                          1    
00148 #define ADC_EOC2                          2    
00149 #define ADC_EOC3                          3    
00150 #define ADC_EOC4                          4    
00151 #define ADC_EOC5                          5    
00152 #define ADC_EOC6                          6    
00153 #define ADC_EOC7                          7    
00154 
00155 #define ADC_OVRE0                         8    
00156 #define ADC_OVRE1                         9    
00157 #define ADC_OVRE2                        10    
00158 #define ADC_OVRE3                        11    
00159 #define ADC_OVRE4                        12    
00160 #define ADC_OVRE5                        13    
00161 #define ADC_OVRE6                        14    
00162 #define ADC_OVRE7                        15    
00163 
00164 #define ADC_DRDY                         16    
00165 #define ADC_GOVRE                        17    
00166 #define ADC_ENDRX                        18    
00167 #define ADC_RXBUFF                       19    
00168 
00169 
00172 #define ADC_LCDR_OFF             0x00000020     
00173 #define ADC_LCDR          (*((reg32_t *)(ADC_BASE + ADC_LCDR_OFF))) 
00174 
00175 
00180 #define ADC_CDR0_OFF              0x00000030    
00181 #define ADC_CDR1_OFF              0x00000034    
00182 #define ADC_CDR2_OFF              0x00000038    
00183 #define ADC_CDR3_OFF              0x0000003C    
00184 #define ADC_CDR4_OFF              0x00000040    
00185 #define ADC_CDR5_OFF              0x00000044    
00186 #define ADC_CDR6_OFF              0x00000048    
00187 #define ADC_CDR7_OFF              0x0000004C    
00188 
00189 #define ADC_CDR0    (*((reg32_t *)(ADC_BASE + ADC_CDR0_OFF)))  
00190 #define ADC_CDR1    (*((reg32_t *)(ADC_BASE + ADC_CDR1_OFF)))  
00191 #define ADC_CDR2    (*((reg32_t *)(ADC_BASE + ADC_CDR2_OFF)))  
00192 #define ADC_CDR3    (*((reg32_t *)(ADC_BASE + ADC_CDR3_OFF)))  
00193 #define ADC_CDR4    (*((reg32_t *)(ADC_BASE + ADC_CDR4_OFF)))  
00194 #define ADC_CDR5    (*((reg32_t *)(ADC_BASE + ADC_CDR5_OFF)))  
00195 #define ADC_CDR6    (*((reg32_t *)(ADC_BASE + ADC_CDR6_OFF)))  
00196 #define ADC_CDR7    (*((reg32_t *)(ADC_BASE + ADC_CDR7_OFF)))  
00197 /* \} */
00198 
00199 #endif /* AT91_ADC_H */