at91sam7.h

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/*
 * Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the copyright holders nor the names of
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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 * For additional information see http://www.ethernut.de/
 */

#ifndef AT91SAM7_H
#define AT91SAM7_H

#include <cfg/compiler.h>

#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7S256
    #define FLASH_BASE      0x100000UL
    #define RAM_BASE        0x200000UL

    #define TC_BASE         0xFFFA0000      
    #define UDP_BASE        0xFFFB0000      
    #define TWI_BASE        0xFFFB8000      
    #define USART0_BASE     0xFFFC0000      
    #define USART1_BASE     0xFFFC4000      
    #define PWMC_BASE       0xFFFCC000      
    #define SSC_BASE        0xFFFD4000      
    #define ADC_BASE        0xFFFD8000      

    #define AIC_BASE        0xFFFFF000      
    #define DBGU_BASE       0xFFFFF200      
    #define PIOA_BASE       0xFFFFF400      
    #define PMC_BASE        0xFFFFFC00      
    #define RSTC_BASE       0xFFFFFD00      
    #define RTT_BASE        0xFFFFFD20      
    #define PIT_BASE        0xFFFFFD30      
    #define WDT_BASE        0xFFFFFD40      
    #define VREG_BASE       0xFFFFFD60      
    #define MC_BASE         0xFFFFFF00      

    #if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
        #define CAN_BASE        0xFFFD0000      
        #define EMAC_BASE       0xFFFDC000      
        #define SPI0_BASE       0xFFFE0000      
        #define SPI1_BASE       0xFFFE4000      
        #define PIOB_BASE       0xFFFFF600      
    #endif

    #if CPU_ARM_AT91SAM7S256
        #define SPI_BASE        0xFFFE0000      
    #endif

    #define PIO_HAS_MULTIDRIVER        1
    #define PIO_HAS_PULLUP             1
    #define PIO_HAS_PERIPHERALSELECT   1
    #define PIO_HAS_OUTPUTWRITEENABLE  1

    #define DBGU_HAS_PDC               1
    #define SPI_HAS_PDC                1
    #define SSC_HAS_PDC                1
    #define USART_HAS_PDC              1

#else
    #error No base addrese register definition for selected ARM CPU

#endif

#include "at91_aic.h"
#include "at91_pit.h"
#include "at91_pmc.h"
#include "at91_mc.h"
#include "at91_wdt.h"
#include "at91_rstc.h"
#include "at91_pio.h"
#include "at91_us.h"
#include "at91_dbgu.h"
#include "at91_tc.h"
#include "at91_adc.h"
#include "at91_pwm.h"
#include "at91_spi.h"
#include "at91_twi.h"
//TODO: add other peripherals

#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X128
    #define FIQ_ID      0       
    #define SYSC_ID     1       
    #define US0_ID      6       
    #define US1_ID      7       
    #define SSC_ID      8       
    #define TWI_ID      9       
    #define PWMC_ID     10      
    #define UDP_ID      11      
    #define TC0_ID      12      
    #define TC1_ID      13      
    #define TC2_ID      14      

    #define IRQ0_ID     30      
    #define IRQ1_ID     31      

    #if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
        #define PIOA_ID     2       
        #define PIOB_ID     3       
        #define SPI0_ID     4       
        #define SPI1_ID     5       
        #define CAN_ID      15      
        #define EMAC_ID     16      
        #define ADC_ID      17      
        /* 18-29 Reserved */

    #endif

    #if CPU_ARM_AT91SAM7S256
        #define PIOA_ID     2       
        /* ID 3 is reserved */
        #define ADC_ID      4       
        #define SPI_ID      5       
        #define SPI0_ID     SPI_ID  
    #endif

#else
    #error No peripheral ID and interrupts definition for selected ARM CPU

#endif
/*\}*/

#if CPU_ARM_AT91SAM7S256
    #define RXD0        5
    #define TXD0        6
    #define RXD1       21
    #define TXD1       22
    #define DTXD       10
    #define DRXD        9
#elif CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
    #define RXD0        0 // PA0
    #define TXD0        1 // PA1
    #define RXD1        5 // PA5
    #define TXD1        6 // PA6
    #define DTXD       28 // PA28
    #define DRXD       27 // PA27
#else
    #error No USART & debug pin names definition for selected ARM CPU
#endif
/*\}*/

#if CPU_ARM_AT91SAM7S256
    #define SPI0_NPCS0      11  // Same as NSS pin.
    #define SPI0_MISO       12
    #define SPI0_MOSI       13
    #define SPI0_SPCK       14

#elif CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
    #define SPI0_NPCS0  12 // Same as NSS pin. PA12
    #define SPI0_NPCS1  13 // PA13
    #define SPI0_NPCS2  14 // PA14
    #define SPI0_NPCS3  15 // PA15
    #define SPI0_MISO   16 // PA16
    #define SPI0_MOSI   17 // PA17
    #define SPI0_SPCK   18 // PA18

    #define SPI1_NPCS0  21 // Same as NSS pin. PA21
    #define SPI1_NPCS1  25 // PA25
    #define SPI1_NPCS2  26 // PA26
    #define SPI1_NPCS3  29 // PA29
    #define SPI1_MISO   24 // PA24
    #define SPI1_MOSI   23 // PA23
    #define SPI1_SPCK   22 // PA22

#else
    #error No SPI pins name definition for selected ARM CPU

#endif
/*\}*/

#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
    #define TIOA0  23 // PB23
    #define TIOB0  24 // PB24
    #define TIOA1  25 // PB25
    #define TIOB1  26 // PB26
    #define TIOA2  27 // PB27
    #define TIOB2  28 // PB28

    #define TIO_PIO_PDR     PIOB_PDR
    #define TIO_PIO_ABSR    PIOB_ASR

#elif CPU_ARM_AT91SAM7S256
    #define TIOA0  0 // PA0
    #define TIOB0  1 // PA1
    #define TIOA1  15 // PA15
    #define TIOB1  16 // PA16
    #define TIOA2  26 // PA26
    #define TIOB2  27 // PA27

    #define TIO_PIO_PDR     PIOA_PDR
    #define TIO_PIO_ABSR    PIOA_BSR

#else
    #error No Timer Counter names of pins definition for selected ARM CPU

#endif
/*\}*/


#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
    #define PWM0  19 // PB19
    #define PWM1  20 // PB20
    #define PWM2  21 // PB21
    #define PWM3  22 // PB22

    #define PWM_PIO_PDR     PIOB_PDR
    #define PWM_PIO_PER     PIOB_PER
    #define PWM_PIO_CODR    PIOB_CODR
    #define PWM_PIO_OER     PIOB_OER
    #define PWM_PIO_ABSR    PIOB_ASR

#elif CPU_ARM_AT91SAM7S256
    #define PWM0  11 // PA11
    #define PWM1  12 // PA12
    #define PWM2  13 // PA13
    #define PWM3  14 // PA14

    #define PWM_PIO_PDR     PIOA_PDR
    #define PWM_PIO_PER     PIOA_PER
    #define PWM_PIO_CODR    PIOA_CODR
    #define PWM_PIO_OER     PIOA_OER
    #define PWM_PIO_ABSR    PIOA_BSR

#else
    #error No PWM names of pins definition for selected ARM CPU

#endif
/*\}*/

#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
    #define TWD  10
    #define TWCK 11

#elif CPU_ARM_AT91SAM7S256
    #define TWD  3    //PA3
    #define TWCK 4    //PA4

#else
    #error No TWI names of pins definition for selected ARM CPU
#endif

#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
    #define ADTRG   18 // PB18
    #define AD0     23 // PB27
    #define AD1     24 // PB28
    #define AD2     25 // PB29
    #define AD3     26 // PB30

#elif CPU_ARM_AT91SAM7S256
    #define ADTRG   18 // PA8
    #define AD0      0 // PA17
    #define AD1      1 // PA18
    #define AD2     15 // PA19
    #define AD3     16 // PA20

#else
    #error No ADC names of pins definition for selected ARM CPU

#endif
/*\}*/

#endif /* AT91SAM7_H */