at91_aic.h

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00001 
00041 /*
00042  * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
00043  *
00044  * Redistribution and use in source and binary forms, with or without
00045  * modification, are permitted provided that the following conditions
00046  * are met:
00047  *
00048  * 1. Redistributions of source code must retain the above copyright
00049  *    notice, this list of conditions and the following disclaimer.
00050  * 2. Redistributions in binary form must reproduce the above copyright
00051  *    notice, this list of conditions and the following disclaimer in the
00052  *    documentation and/or other materials provided with the distribution.
00053  * 3. Neither the name of the copyright holders nor the names of
00054  *    contributors may be used to endorse or promote products derived
00055  *    from this software without specific prior written permission.
00056  *
00057  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00058  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00059  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00060  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00061  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00062  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00063  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00064  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00065  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00066  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00067  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00068  * SUCH DAMAGE.
00069  *
00070  * For additional information see http://www.ethernut.de/
00071  */
00072 
00073 #ifndef AT91_AIC_H
00074 #define AT91_AIC_H
00075 
00076 #include <cfg/compiler.h>
00077 
00078 
00079 
00083 #define AIC_SMR(i)  (*((reg32_t *)(AIC_BASE + (i) * 4)))
00084 
00089 #define AIC_PRIOR_MASK 0x00000007
00090 
00098 /*\{*/
00099 #define AIC_SRCTYPE_MASK 0x00000060
00100 
00101 #define AIC_SRCTYPE_INT_LEVEL_SENSITIVE 0x00000000      
00102 #define AIC_SRCTYPE_INT_EDGE_TRIGGERED  0x00000020      
00103 #define AIC_SRCTYPE_EXT_LOW_LEVEL       0x00000000      
00104 #define AIC_SRCTYPE_EXT_NEGATIVE_EDGE   0x00000020      
00105 #define AIC_SRCTYPE_EXT_HIGH_LEVEL      0x00000040      
00106 #define AIC_SRCTYPE_EXT_POSITIVE_EDGE   0x00000060      
00107 /*\}*/
00108 
00109 
00113 typedef void (*irq_handler_t)(void);
00114 
00116 /*\{*/
00121 #define AIC_SVR(i)  (*((volatile irq_handler_t *)(AIC_BASE + 0x80 + (i) * 4)))
00122 /*\}*/
00123 
00125 /*\{*/
00126 #define AIC_IVR_OFF 0x00000100  
00127 #define AIC_IVR     (*((reg32_t *)(AIC_BASE + AIC_IVR_OFF))) 
00128 /*\}*/
00129 
00131 /*\{*/
00132 #define AIC_FVR_OFF 0x00000104  
00133 #define AIC_FVR     (*((reg32_t *)(AIC_BASE + AIC_FVR_OFF))) 
00134 /*\}*/
00135 
00137 /*\{*/
00138 #define AIC_ISR_OFF    0x00000108  
00139 #define AIC_ISR        (*((reg32_t *)(AIC_BASE + AIC_ISR_OFF))) 
00140 #define AIC_IRQID_MASK 0x0000001F  
00141 /*\}*/
00142 
00144 /*\{*/
00145 #define AIC_IPR_OFF 0x0000010C  
00146 #define AIC_IPR     (*((reg32_t *)(AIC_BASE + AIC_IPR_OFF))) 
00147 /*\}*/
00148 
00150 /*\{*/
00151 #define AIC_IMR_OFF 0x00000110  
00152 #define AIC_IMR     (*((reg32_t *)(AIC_BASE + AIC_IMR_OFF))) 
00153 /*\}*/
00154 
00156 /*\{*/
00157 #define AIC_CISR_OFF 0x00000114  
00158 #define AIC_CISR     (*((reg32_t *)(AIC_BASE + AIC_CISR_OFF))) 
00159 #define AIC_NFIQ     1  
00160 #define AIC_NIRQ     2  
00161 /*\}*/
00162 
00164 /*\{*/
00165 #define AIC_IECR_OFF 0x00000120  
00166 #define AIC_IECR     (*((reg32_t *)(AIC_BASE + AIC_IECR_OFF)))   
00167 /*\}*/
00168 
00170 /*\{*/
00171 #define AIC_IDCR_OFF 0x00000124  
00172 #define AIC_IDCR     (*((reg32_t *)(AIC_BASE + AIC_IDCR_OFF)))   
00173 /*\}*/
00174 
00176 /*\{*/
00177 #define AIC_ICCR_OFF 0x00000128  
00178 #define AIC_ICCR     (*((reg32_t *)(AIC_BASE + AIC_ICCR_OFF)))   
00179 /*\}*/
00180 
00182 /*\{*/
00183 #define AIC_ISCR_OFF 0x0000012C  
00184 #define AIC_ISCR     (*((reg32_t *)(AIC_BASE + AIC_ISCR_OFF)))   
00185 /*\}*/
00186 
00188 /*\{*/
00189 #define AIC_EOICR_OFF 0x00000130  
00190 #define AIC_EOICR     (*((reg32_t *)(AIC_BASE + AIC_EOICR_OFF)))  
00191 /*\}*/
00192 
00194 /*\{*/
00195 #define AIC_SPU_OFF 0x00000134  
00196 #define AIC_SPU     (*((reg32_t *)(AIC_BASE + AIC_SPU_OFF)==    
00197 /*\}*/
00198 
00200 /*\{*/
00201 #define AIC_DCR_OFF 0x0000138   
00202 #define AIC_DCR     (*((reg32_t *)(AIC_BASE + AIC_DCR_OFF)))    
00203 /*\}*/
00204 
00206 /*\{*/
00207 #define AIC_FFER_OFF 0x00000140  
00208 #define AIC_FFER     (*((reg32_t *)(AIC_BASE + AIC_FFER_OFF)))   
00209 /*\}*/
00210 
00212 /*\{*/
00213 #define AIC_FFDR_OFF 0x00000144  
00214 #define AIC_FFDR     (*((reg32_t *)(AIC_BASE + AIC_FFDR_OFF)))   
00215 /*\}*/
00216 
00218 /*\{*/
00219 #define AIC_FFSR_OFF 0x00000148  
00220 #define AIC_FFSR     (*((reg32_t *)(AIC_BASE + AIC_FFSR_OFF)))   
00221 /*\}*/
00222 
00223 #endif /* AT91_AIC_H */