at91_tc.h File Reference

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Defines
#define	TC_TC0_OFF   0x00000000
	Timer Counter Control Register.
#define	TC_TC1_OFF   0x00000040
	Channel 1 control register offset.
#define	TC_TC2_OFF   0x00000080
	Channel 2 control register offset.
#define	TC0_CCR   (*((reg32_t *)(TC_BASE + TC_TC0_OFF)))
	Channel 0 control register address.
#define	TC1_CCR   (*((reg32_t *)(TC_BASE + TC_TC1_OFF)))
	Channel 1 control register address.
#define	TC2_CCR   (*((reg32_t *)(TC_BASE + TC_TC2_OFF)))
	Channel 2 control register address.
#define	TC_CLKEN   0
	Clock enable command.
#define	TC_CLKDIS   1
	Clock disable command.
#define	TC_SWTRG   2
	Software trigger command.
#define	TC_CMR_OFF   0x00000004
	Timer Counter Channel Mode Register.
#define	TC0_CMR   (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_CMR_OFF)))
	Channel 0 mode register address.
#define	TC1_CMR   (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_CMR_OFF)))
	Channel 1 mode register address.
#define	TC2_CMR   (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_CMR_OFF)))
	Channel 2 mode register address.
#define	TC_CLKS_MASK   0x00000007
	Clock selection mask.
#define	TC_CLKS_MCK2   0x00000000
	Selects MCK / 2.
#define	TC_CLKS_MCK8   0x00000001
	Selects MCK / 8.
#define	TC_CLKS_MCK32   0x00000002
	Selects MCK / 32.
#define	TC_CLKS_MCK128   0x00000003
	Selects MCK / 128.
#define	TC_CLKS_MCK1024   0x00000004
	Selects MCK / 1024.
#define	TC_CLKS_XC0   0x00000005
	Selects external clock 0.
#define	TC_CLKS_XC1   0x00000006
	Selects external clock 1.
#define	TC_CLKS_XC2   0x00000007
	Selects external clock 2.
#define	TC_CLKI   3
	Increments on falling edge.
#define	TC_BURST_MASK   0x00000030
	Burst signal selection mask.
#define	TC_BURST_NONE   0x00000000
	Clock is not gated by an external signal.
#define	TC_BUSRT_XC0   0x00000010
	ANDed with external clock 0.
#define	TC_BURST_XC1   0x00000020
	ANDed with external clock 1.
#define	TC_BURST_XC2   0x00000030
	ANDed with external clock 2.
#define	TC_WAVE   15
	Selects waveform mode.
#define	TC_CPCTRG   14
	Capture Mode.
#define	TC_LDBSTOP   6
	Counter clock stopped on RB loading.
#define	TC_LDBDIS   7
	Counter clock disabled on RB loading.
#define	TC_ETRGEDG_MASK   0x00000300
	External trigger edge selection mask.
#define	TC_ETRGEDG_RISING_EDGE   0x00000100
	Trigger on external rising edge.
#define	TC_ETRGEDG_FALLING_EDGE   0x00000200
	Trigger on external falling edge.
#define	TC_ETRGEDG_BOTH_EDGE   0x00000300
	Trigger on both external edges.
#define	TC_ABETRG_MASK   0x00000400
	TIOA or TIOB external trigger selection mask.
#define	TC_ABETRG_TIOA   10
	TIOA used as an external trigger.
#define	TC_LDRA_MASK   0x00030000
	RA loading selection mask.
#define	TC_LDRA_RISING_EDGE   0x00010000
	Load RA on rising edge of TIOA.
#define	TC_LDRA_FALLING_EDGE   0x00020000
	Load RA on falling edge of TIOA.
#define	TC_LDRA_BOTH_EDGE   0x00030000
	Load RA on any edge of TIOA.
#define	TC_LDRB_MASK   0x000C0000
	RB loading selection mask.
#define	TC_LDRB_RISING_EDGE   0x00040000
	Load RB on rising edge of TIOA.
#define	TC_LDRB_FALLING_EDGE   0x00080000
	Load RB on falling edge of TIOA.
#define	TC_LDRB_BOTH_EDGE   0x000C0000
	Load RB on any edge of TIOA.
#define	TC_CPCSTOP   6
	Waveform Mode.
#define	TC_CPCDIS   7
	Counter clock disabled on RC compare.
#define	TC_EEVTEDG_MASK   0x00000300
	External event edge selection mask.
#define	TC_EEVTEDG_RISING_EDGE   0x00000100
	External event on rising edge..
#define	TC_EEVTEDG_FALLING_EDGE   0x00000200
	External event on falling edge..
#define	TC_EEVTEDG_BOTH_EDGE   0x00000300
	External event on any edge..
#define	TC_EEVT_MASK   0x00000C00
	External event selection mask.
#define	TC_EEVT_TIOB   0x00000000
	TIOB selected as external event.
#define	TC_EEVT_XC0   0x00000400
	XC0 selected as external event.
#define	TC_EEVT_XC1   0x00000800
	XC1 selected as external event.
#define	TC_EEVT_XC2   0x00000C00
	XC2 selected as external event.
#define	TC_ENETRG   12
	External event trigger enable.
#define	TC_WAVSEL_MASK   0x00006000
	Waveform selection mask.
#define	TC_WAVSEL_UP   0x00000000
	UP mode whitout automatic trigger on RC compare.
#define	TC_WAVSEL_UP_RC_TRG   0x00004000
	UP mode whit automatic trigger on RC compare.
#define	TC_WAVSEL_UPDOWN   0x00002000
	UPDOWN mode whitout automatic trigger on RC compare.
#define	TC_WAVSEL_UPDOWN_RC_TRG   0x00003000
	UPDOWN mode whit automatic trigger on RC compare.
#define	TC_ACPA_MASK   0x00030000
	Masks RA compare effect on TIOA.
#define	TC_ACPA_SET_OUTPUT   0x00010000
	RA compare sets TIOA.
#define	TC_ACPA_CLEAR_OUTPUT   0x00020000
	RA compare clears TIOA.
#define	TC_ACPA_TOGGLE_OUTPUT   0x00030000
	RA compare toggles TIOA.
#define	TC_ACPC_MASK   0x000C0000
	Masks RC compare effect on TIOA.
#define	TC_ACPC_SET_OUTPUT   0x00040000
	RC compare sets TIOA.
#define	TC_ACPC_CLEAR_OUTPUT   0x00080000
	RC compare clears TIOA.
#define	TC_ACPC_TOGGLE_OUTPUT   0x000C0000
	RC compare toggles TIOA.
#define	TC_AEEVT_MASK   0x00300000
	Masks external event effect on TIOA.
#define	TC_AEEVT_SET_OUTPUT   0x00100000
	External event sets TIOA.
#define	TC_AEEVT_CLEAR_OUTPUT   0x00200000
	External event clears TIOA.
#define	TC_AEEVT_TOGGLE_OUTPUT   0x00300000
	External event toggles TIOA.
#define	TC_ASWTRG_MASK   0x00C00000
	Masks software trigger effect on TIOA.
#define	TC_ASWTRG_SET_OUTPUT   0x00400000
	Software trigger sets TIOA.
#define	TC_ASWTRG_CLEAR_OUTPUT   0x00800000
	Software trigger clears TIOA.
#define	TC_ASWTRG_TOGGLE_OUTPUT   0x00C00000
	Software trigger toggles TIOA.
#define	TC_BCPB_MASK   0x03000000
	Masks RB compare effect on TIOB.
#define	TC_BCPB_SET_OUTPUT   0x01000000
	RB compare sets TIOB.
#define	TC_BCPB_CLEAR_OUTPUT   0x02000000
	RB compare clears TIOB.
#define	TC_BCPB_TOGGLE_OUTPUT   0x03000000
	RB compare toggles TIOB.
#define	TC_BCPC_MASK   0x0C000000
	Masks RC compare effect on TIOB.
#define	TC_BCPC_SET_OUTPUT   0x04000000
	RC compare sets TIOB.
#define	TC_BCPC_CLEAR_OUTPUT   0x08000000
	RC compare clears TIOB.
#define	TC_BCPC_TOGGLE_OUTPUT   0x0C000000
	RC compare toggles TIOB.
#define	TC_BEEVT_MASK   0x30000000
	Masks external event effect on TIOB.
#define	TC_BEEVT_SET_OUTPUT   0x10000000
	External event sets TIOB.
#define	TC_BEEVT_CLEAR_OUTPUT   0x20000000
	External event clears TIOB.
#define	TC_BEEVT_TOGGLE_OUTPUT   0x30000000
	External event toggles TIOB.
#define	TC_BSWTRG_MASK   0xC0000000
	Masks software trigger effect on TIOB.
#define	TC_BSWTRG_SET_OUTPUT   0x40000000
	Software trigger sets TIOB.
#define	TC_BSWTRG_CLEAR_OUTPUT   0x80000000
	Software trigger clears TIOB.
#define	TC_BSWTRG_TOGGLE_OUTPUT   0xC0000000
	Software trigger toggles TIOB.
#define	TC_CV_OFF   0x00000010
	Counter Value Register.
#define	TC0_CV   (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_CV_OFF)))
	Counter 0 value.
#define	TC1_CV   (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_CV_OFF)))
	Counter 1 value.
#define	TC2_CV   (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_CV_OFF)))
	Counter 2 value.
#define	TC_RA_OFF   0x00000014
	Timer Counter Register A.
#define	TC0_RA   (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_RA_OFF)))
	Channel 0 register A.
#define	TC1_RA   (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_RA_OFF)))
	Channel 1 register A.
#define	TC2_RA   (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_RA_OFF)))
	Channel 2 register A.
#define	TC_RB_OFF   0x00000018
	Timer Counter Register B.
#define	TC0_RB   (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_RB_OFF)))
	Channel 0 register B.
#define	TC1_RB   (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_RB_OFF)))
	Channel 1 register B.
#define	TC2_RB   (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_RB_OFF)))
	Channel 2 register B.
#define	TC_RC_OFF   0x0000001C
	Timer Counter Register C.
#define	TC0_RC   (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_RC_OFF)))
	Channel 0 register C.
#define	TC1_RC   (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_RC_OFF)))
	Channel 1 register C.
#define	TC2_RC   (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_RC_OFF)))
	Channel 2 register C.
#define	TC_SR_OFF   0x00000020
	Timer Counter Status and Interrupt Registers.
#define	TC0_SR   (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_SR_OFF)))
	Status register address.
#define	TC1_SR   (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_SR_OFF)))
	Status register address.
#define	TC2_SR   (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_SR_OFF)))
	Status register address.
#define	TC_IER_OFF   0x00000024
	Interrupt Enable Register offset.
#define	TC0_IER   (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_IER_OFF)))
	Channel 0 interrupt enable register address.
#define	TC1_IER   (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_IER_OFF)))
	Channel 1 interrupt enable register address.
#define	TC2_IER   (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_IER_OFF)))
	Channel 2 interrupt enable register address.
#define	TC_IDR_OFF   0x00000028
	Interrupt Disable Register offset.
#define	TC0_IDR   (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_IDR_OFF)))
	Channel 0 interrupt disable register address.
#define	TC1_IDR   (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_IDR_OFF)))
	Channel 1 interrupt disable register address.
#define	TC2_IDR   (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_IDR_OFF)))
	Channel 2 interrupt disable register address.
#define	TC_IMR_OFF   0x0000002C
	Interrupt Mask Register offset.
#define	TC0_IMR   (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_IMR_OFF)))
	Channel 0 interrupt mask register address.
#define	TC1_IMR   (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_IMR_OFF)))
	Channel 1 interrupt mask register address.
#define	TC2_IMR   (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_IMR_OFF)))
	Channel 2 interrupt mask register address.
#define	TC_COVFS   0
	Counter overflow flag.
#define	TC_LOVRS   1
	Load overrun flag.
#define	TC_CPAS   2
	RA compare flag.
#define	TC_CPBS   3
	RB compare flag.
#define	TC_CPCS   4
	RC compare flag.
#define	TC_LDRAS   5
	RA loading flag.
#define	TC_LDRBS   6
	RB loading flag.
#define	TC_ETRGS   7
	External trigger flag.
#define	TC_CLKSTA   16
	Clock enable flag.
#define	TC_MTIOA   17
	TIOA flag.
#define	TC_MTIOB   18
	TIOB flag.
#define	TC_BCR_OFF   0x000000C0
	Timer Counter Block Control Register.
#define	TC_BCR   (*((reg32_t *)(TC_BASE + TC_BCR_OFF)))
	Block control register address.
#define	TC_SYNC   0
	Synchronisation trigger.
#define	TC_BMR_OFF   0x000000C4
	Timer Counter Block Mode Register.
#define	TC_BMR   (*((reg32_t *)(TC_BASE + TC_BMR_OFF)))
	Block mode register address.
#define	TC_TC0XC0S   0x00000003
	External clock signal 0 selection mask.
#define	TC_TCLK0XC0   0x00000000
	Selects TCLK0.
#define	TC_NONEXC0   0x00000001
	None selected.
#define	TC_TIOA1XC0   0x00000002
	Selects TIOA1.
#define	TC_TIOA2XC0   0x00000003
	Selects TIOA2.
#define	TC_TC1XC1S   0x0000000C
	External clock signal 1 selection mask.
#define	TC_TCLK1XC1   0x00000000
	Selects TCLK1.
#define	TC_NONEXC1   0x00000004
	None selected.
#define	TC_TIOA0XC1   0x00000008
	Selects TIOA0.
#define	TC_TIOA2XC1   0x0000000C
	Selects TIOA2.
#define	TC_TC2XC2S   0x00000030
	External clock signal 2 selection mask.
#define	TC_TCLK2XC2   0x00000000
	Selects TCLK2.
#define	TC_NONEXC2   0x00000010
	None selected.
#define	TC_TIOA0XC2   0x00000020
	Selects TIOA0.
#define	TC_TIOA1XC2   0x00000030
	Selects TIOA1.

---

Detailed Description

Version:

Id

at91_tc.h 1239 2008-04-30 15:09:58Z asterix

Author:

Daniele Basile <asterix@develer.com>

AT91SAM7 Conunter timer definition. This file is based on NUT/OS implementation. See license below.

Definition in file at91_tc.h.

---

Define Documentation

#define TC_BCR_OFF   0x000000C0

Timer Counter Block Control Register.

Block control register offset.

Definition at line 292 of file at91_tc.h.

#define TC_BMR_OFF   0x000000C4

Timer Counter Block Mode Register.

Block mode register offset.

Definition at line 300 of file at91_tc.h.

#define TC_CMR_OFF   0x00000004

Timer Counter Channel Mode Register.

Mode register offset.

Definition at line 93 of file at91_tc.h.

#define TC_CPCSTOP   6

Waveform Mode.

Counter clock stopped on RC compare.

Definition at line 154 of file at91_tc.h.

#define TC_CPCTRG   14

Capture Mode.

RC Compare Enable Trigger Enable.

Definition at line 125 of file at91_tc.h.

#define TC_CV_OFF   0x00000010

Counter Value Register.

Counter register value offset.

Definition at line 220 of file at91_tc.h.

#define TC_RA_OFF   0x00000014

Timer Counter Register A.

Register A offset.

Definition at line 228 of file at91_tc.h.

#define TC_RB_OFF   0x00000018

Timer Counter Register B.

Register B offset.

Definition at line 237 of file at91_tc.h.

#define TC_RC_OFF   0x0000001C

Timer Counter Register C.

Register C offset.

Definition at line 246 of file at91_tc.h.

#define TC_SR_OFF   0x00000020

Timer Counter Status and Interrupt Registers.

Status Register offset.

Definition at line 256 of file at91_tc.h.

#define TC_TC0_OFF   0x00000000

Timer Counter Control Register.

Channel 0 control register offset.

Definition at line 80 of file at91_tc.h.