i2c_avr.c

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#include <hw/hw_cpufreq.h>  /* CPU_FREQ */

#include "cfg/cfg_i2c.h"

#define LOG_LEVEL  I2C_LOG_LEVEL
#define LOG_FORMAT I2C_LOG_FORMAT

#include <cfg/log.h>

#include <cfg/debug.h>
#include <cfg/macros.h> // BV()
#include <cfg/module.h>

#include <cpu/detect.h>
#include <cpu/irq.h>
#include <drv/timer.h>
#include <drv/i2c.h>

#include <compat/twi.h>


/* Wait for TWINT flag set: bus is ready */
#define WAIT_TWI_READY  do {} while (!(TWCR & BV(TWINT)))

static bool i2c_builtin_start(void)
{
    TWCR = BV(TWINT) | BV(TWSTA) | BV(TWEN);
    WAIT_TWI_READY;

    if (TW_STATUS == TW_START || TW_STATUS == TW_REP_START)
        return true;

    LOG_ERR("!TW_(REP)START: %x\n", TWSR);
    return false;
}


bool i2c_builtin_start_w(uint8_t id)
{
    /*
     * Loop on the select write sequence: when the eeprom is busy
     * writing previously sent data it will reply to the SLA_W
     * control byte with a NACK.  In this case, we must
     * keep trying until the eeprom responds with an ACK.
     */
    ticks_t start = timer_clock();
    while (i2c_builtin_start())
    {
        TWDR = id & ~I2C_READBIT;
        TWCR = BV(TWINT) | BV(TWEN);
        WAIT_TWI_READY;

        if (TW_STATUS == TW_MT_SLA_ACK)
            return true;
        else if (TW_STATUS != TW_MT_SLA_NACK)
        {
            LOG_ERR("!TW_MT_SLA_(N)ACK: %x\n", TWSR);
            break;
        }
        else if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
        {
            LOG_ERR("Timeout on TWI_MT_START\n");
            break;
        }
    }

    return false;
}


bool i2c_builtin_start_r(uint8_t id)
{
    if (i2c_builtin_start())
    {
        TWDR = id | I2C_READBIT;
        TWCR = BV(TWINT) | BV(TWEN);
        WAIT_TWI_READY;

        if (TW_STATUS == TW_MR_SLA_ACK)
            return true;

        LOG_ERR("!TW_MR_SLA_ACK: %x\n", TWSR);
    }

    return false;
}


void i2c_builtin_stop(void)
{
        TWCR = BV(TWINT) | BV(TWEN) | BV(TWSTO);
}


bool i2c_builtin_put(const uint8_t data)
{
    TWDR = data;
    TWCR = BV(TWINT) | BV(TWEN);
    WAIT_TWI_READY;
    if (TW_STATUS != TW_MT_DATA_ACK)
    {
        LOG_ERR("!TW_MT_DATA_ACK: %x\n", TWSR);
        return false;
    }
    return true;
}

int i2c_builtin_get(bool ack)
{
    TWCR = BV(TWINT) | BV(TWEN) | (ack ? BV(TWEA) : 0);
    WAIT_TWI_READY;

    if (ack)
    {
        if (TW_STATUS != TW_MR_DATA_ACK)
        {
            LOG_ERR("!TW_MR_DATA_ACK: %x\n", TWSR);
            return EOF;
        }
    }
    else
    {
        if (TW_STATUS != TW_MR_DATA_NACK)
        {
            LOG_ERR("!TW_MR_DATA_NACK: %x\n", TWSR);
            return EOF;
        }
    }

    /* avoid sign extension */
    return (int)(uint8_t)TWDR;
}

MOD_DEFINE(i2c);

void i2c_builtin_init(void)
{
    ATOMIC(
        /*
         * This is pretty useless according to AVR's datasheet,
         * but it helps us driving the TWI data lines on boards
         * where the bus pull-up resistors are missing.  This is
         * probably due to some unwanted interaction between the
         * port pin and the TWI lines.
         */
#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
        PORTD |= BV(PD0) | BV(PD1);
        DDRD  |= BV(PD0) | BV(PD1);
#elif CPU_AVR_ATMEGA8
        PORTC |= BV(PC4) | BV(PC5);
        DDRC  |= BV(PC4) | BV(PC5);
#elif CPU_AVR_ATMEGA32
        PORTC |= BV(PC1) | BV(PC0);
        DDRC  |= BV(PC1) | BV(PC0);
#else
        #error Unsupported architecture
#endif

        /*
         * Set speed:
         * F = CPU_FREQ / (16 + 2*TWBR * 4^TWPS)
         */
        #ifndef CONFIG_I2C_FREQ
            #warning Using default value of 300000L for CONFIG_I2C_FREQ
            #define CONFIG_I2C_FREQ  300000L /* ~300 kHz */
        #endif
        #define TWI_PRESC 1       /* 4 ^ TWPS */

        TWBR = (CPU_FREQ / (2 * CONFIG_I2C_FREQ * TWI_PRESC)) - (8 / TWI_PRESC);
        TWSR = 0;
        TWCR = BV(TWEN);
    );
    MOD_INIT(i2c);
}