timer_at91.h

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00001 
00040 #ifndef DRV_AT91_TIMER_H
00041 #define DRV_AT91_TIMER_H
00042 
00043 #include <hw/hw_cpufreq.h>     /* CPU_FREQ */
00044 
00045 #include "cfg/cfg_timer.h"     /* CONFIG_TIMER */
00046 #include <cfg/compiler.h>      /* uint8_t */
00047 #include <cfg/macros.h>        /* BV */
00048 
00049 #include <io/arm.h>
00050 
00058 #define TIMER_ON_PIT 1  
00059 
00060 #define TIMER_DEFAULT TIMER_ON_PIT  
00061 
00062 /*
00063  * Hardware dependent timer initialization.
00064  */
00065 #if (CONFIG_TIMER == TIMER_ON_PIT)
00066 
00067     /*
00068      * On ARM all system IRQs are handled by the sysirq_dispatcher, so the actual
00069      * timer handler can be treated like any other normal routine.
00070      */
00071     #define DEFINE_TIMER_ISR    void timer_handler(void);   \
00072                     void timer_handler(void)
00073 
00074     #define TIMER_TICKS_PER_SEC  1000
00075     #define TIMER_HW_CNT         (CPU_FREQ / (16 * TIMER_TICKS_PER_SEC) - 1)
00076 
00078     #define TIMER_HW_HPTICKS_PER_SEC (CPU_FREQ / 16)
00079 
00081     typedef uint32_t hptime_t;
00082     #define SIZEOF_HPTIME_T 4
00083 
00084     INLINE void timer_hw_irq(void)
00085     {
00086         /* Reset counters, this is needed to reset timer and interrupt flags */
00087         uint32_t dummy = PIVR;
00088         (void) dummy;
00089     }
00090 
00091     INLINE bool timer_hw_triggered(void)
00092     {
00093         return PIT_SR & BV(PITS);
00094     }
00095 
00096     INLINE hptime_t timer_hw_hpread(void)
00097     {
00098         /* In the upper part of PIT_PIIR there is unused data */
00099         return PIIR & CPIV_MASK;
00100     }
00101 
00102 #else
00103 
00104     #error Unimplemented value for CONFIG_TIMER
00105 #endif /* CONFIG_TIMER */
00106 
00107 void timer_hw_init(void);
00108 
00109 
00110 #endif /* DRV_TIMER_AT91_H */