at91_rstc.h

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/*
 * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
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 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
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#ifndef AT91_RTSC_H
#define AT91_RTSC_H

/*\{*/
#define RSTC_CR         (*((reg32_t *)(RSTC_BASE + 0x00)))      ///< Reset controller control register address.
#define RSTC_PROCRST                     0  ///< Processor reset.
#define RSTC_PERRST                      2  ///< Peripheral reset.
#define RSTC_EXTRST                      3  ///< External reset.
#define RSTC_KEY                0xA5000000  ///< Password.
/*\}*/

/*\{*/
#define RSTC_SR         (*((reg32_t *)(RSTC_BASE + 0x04)))      ///< Reset controller status register address.
#define RSTC_URSTS                       0  ///< User reset status.
#define RSTC_BODSTS                      1  ///< Brownout detection status.
#define RSTC_RSTTYP_MASK        0x00000700  ///< Reset type.
#define RSTC_RSTTYP_POWERUP     0x00000000  ///< Power-up reset.
//#define RSTC_RSTTYP_WAKEUP      0x00000100      ///< VDDCORE rising.
#define RSTC_RSTTYP_WATCHDOG    0x00000200  ///< Watchdog reset.
#define RSTC_RSTTYP_SOFTWARE    0x00000300  ///< Software reset.
#define RSTC_RSTTYP_USER        0x00000400  ///< User reset.
#define RSTC_RSTTYP_BROWNOUT    0x00000500  ///< Brownout reset.
#define RSTC_NRSTL                      16  ///< NRST pin level.
#define RSTC_SRCMP                      17  ///< Software reset command in progress.
/*\}*/

/*\{*/
#define RSTC_MR         (*((reg32_t *)(RSTC_BASE + 0x08)))      ///< Reset controller mode register address.
#define RSTC_URSTEN                      0  ///< User reset enable.
#define RSTC_URSTIEN                     4  ///< User reset interrupt enable.
#define RSTC_ERSTL_MASK         0x00000F00  ///< External reset length.
#define RSTC_ERSTL_SHIFT                 8  ///< Least significant bit of external reset length.
#define RSTC_BODIEN                     16  ///< Brown-out detection interrupt enable.
/*\}*/


#endif /* AT91_RTSC_H */