lm3s1968.h
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00036 #ifndef LM3S1968_H
00037 #define LM3S1968_H
00038
00039 #include <cfg/compiler.h>
00040
00044
00045 #define WATCHDOG0_LOAD_R (*((reg32_t *)0x40000000))
00046 #define WATCHDOG0_VALUE_R (*((reg32_t *)0x40000004))
00047 #define WATCHDOG0_CTL_R (*((reg32_t *)0x40000008))
00048 #define WATCHDOG0_ICR_R (*((reg32_t *)0x4000000C))
00049 #define WATCHDOG0_RIS_R (*((reg32_t *)0x40000010))
00050 #define WATCHDOG0_MIS_R (*((reg32_t *)0x40000014))
00051 #define WATCHDOG0_TEST_R (*((reg32_t *)0x40000418))
00052 #define WATCHDOG0_LOCK_R (*((reg32_t *)0x40000C00))
00053
00054
00058
00059 #define GPIO_PORTA_DATA_BITS_R ((reg32_t *)0x40004000)
00060 #define GPIO_PORTA_DATA_R (*((reg32_t *)0x400043FC))
00061 #define GPIO_PORTA_DIR_R (*((reg32_t *)0x40004400))
00062 #define GPIO_PORTA_IS_R (*((reg32_t *)0x40004404))
00063 #define GPIO_PORTA_IBE_R (*((reg32_t *)0x40004408))
00064 #define GPIO_PORTA_IEV_R (*((reg32_t *)0x4000440C))
00065 #define GPIO_PORTA_IM_R (*((reg32_t *)0x40004410))
00066 #define GPIO_PORTA_RIS_R (*((reg32_t *)0x40004414))
00067 #define GPIO_PORTA_MIS_R (*((reg32_t *)0x40004418))
00068 #define GPIO_PORTA_ICR_R (*((reg32_t *)0x4000441C))
00069 #define GPIO_PORTA_AFSEL_R (*((reg32_t *)0x40004420))
00070 #define GPIO_PORTA_DR2R_R (*((reg32_t *)0x40004500))
00071 #define GPIO_PORTA_DR4R_R (*((reg32_t *)0x40004504))
00072 #define GPIO_PORTA_DR8R_R (*((reg32_t *)0x40004508))
00073 #define GPIO_PORTA_ODR_R (*((reg32_t *)0x4000450C))
00074 #define GPIO_PORTA_PUR_R (*((reg32_t *)0x40004510))
00075 #define GPIO_PORTA_PDR_R (*((reg32_t *)0x40004514))
00076 #define GPIO_PORTA_SLR_R (*((reg32_t *)0x40004518))
00077 #define GPIO_PORTA_DEN_R (*((reg32_t *)0x4000451C))
00078 #define GPIO_PORTA_LOCK_R (*((reg32_t *)0x40004520))
00079 #define GPIO_PORTA_CR_R (*((reg32_t *)0x40004524))
00080
00081
00085
00086 #define GPIO_PORTB_DATA_BITS_R ((reg32_t *)0x40005000)
00087 #define GPIO_PORTB_DATA_R (*((reg32_t *)0x400053FC))
00088 #define GPIO_PORTB_DIR_R (*((reg32_t *)0x40005400))
00089 #define GPIO_PORTB_IS_R (*((reg32_t *)0x40005404))
00090 #define GPIO_PORTB_IBE_R (*((reg32_t *)0x40005408))
00091 #define GPIO_PORTB_IEV_R (*((reg32_t *)0x4000540C))
00092 #define GPIO_PORTB_IM_R (*((reg32_t *)0x40005410))
00093 #define GPIO_PORTB_RIS_R (*((reg32_t *)0x40005414))
00094 #define GPIO_PORTB_MIS_R (*((reg32_t *)0x40005418))
00095 #define GPIO_PORTB_ICR_R (*((reg32_t *)0x4000541C))
00096 #define GPIO_PORTB_AFSEL_R (*((reg32_t *)0x40005420))
00097 #define GPIO_PORTB_DR2R_R (*((reg32_t *)0x40005500))
00098 #define GPIO_PORTB_DR4R_R (*((reg32_t *)0x40005504))
00099 #define GPIO_PORTB_DR8R_R (*((reg32_t *)0x40005508))
00100 #define GPIO_PORTB_ODR_R (*((reg32_t *)0x4000550C))
00101 #define GPIO_PORTB_PUR_R (*((reg32_t *)0x40005510))
00102 #define GPIO_PORTB_PDR_R (*((reg32_t *)0x40005514))
00103 #define GPIO_PORTB_SLR_R (*((reg32_t *)0x40005518))
00104 #define GPIO_PORTB_DEN_R (*((reg32_t *)0x4000551C))
00105 #define GPIO_PORTB_LOCK_R (*((reg32_t *)0x40005520))
00106 #define GPIO_PORTB_CR_R (*((reg32_t *)0x40005524))
00107
00108
00112
00113 #define GPIO_PORTC_DATA_BITS_R ((reg32_t *)0x40006000)
00114 #define GPIO_PORTC_DATA_R (*((reg32_t *)0x400063FC))
00115 #define GPIO_PORTC_DIR_R (*((reg32_t *)0x40006400))
00116 #define GPIO_PORTC_IS_R (*((reg32_t *)0x40006404))
00117 #define GPIO_PORTC_IBE_R (*((reg32_t *)0x40006408))
00118 #define GPIO_PORTC_IEV_R (*((reg32_t *)0x4000640C))
00119 #define GPIO_PORTC_IM_R (*((reg32_t *)0x40006410))
00120 #define GPIO_PORTC_RIS_R (*((reg32_t *)0x40006414))
00121 #define GPIO_PORTC_MIS_R (*((reg32_t *)0x40006418))
00122 #define GPIO_PORTC_ICR_R (*((reg32_t *)0x4000641C))
00123 #define GPIO_PORTC_AFSEL_R (*((reg32_t *)0x40006420))
00124 #define GPIO_PORTC_DR2R_R (*((reg32_t *)0x40006500))
00125 #define GPIO_PORTC_DR4R_R (*((reg32_t *)0x40006504))
00126 #define GPIO_PORTC_DR8R_R (*((reg32_t *)0x40006508))
00127 #define GPIO_PORTC_ODR_R (*((reg32_t *)0x4000650C))
00128 #define GPIO_PORTC_PUR_R (*((reg32_t *)0x40006510))
00129 #define GPIO_PORTC_PDR_R (*((reg32_t *)0x40006514))
00130 #define GPIO_PORTC_SLR_R (*((reg32_t *)0x40006518))
00131 #define GPIO_PORTC_DEN_R (*((reg32_t *)0x4000651C))
00132 #define GPIO_PORTC_LOCK_R (*((reg32_t *)0x40006520))
00133 #define GPIO_PORTC_CR_R (*((reg32_t *)0x40006524))
00134
00135
00139
00140 #define GPIO_PORTD_DATA_BITS_R ((reg32_t *)0x40007000)
00141 #define GPIO_PORTD_DATA_R (*((reg32_t *)0x400073FC))
00142 #define GPIO_PORTD_DIR_R (*((reg32_t *)0x40007400))
00143 #define GPIO_PORTD_IS_R (*((reg32_t *)0x40007404))
00144 #define GPIO_PORTD_IBE_R (*((reg32_t *)0x40007408))
00145 #define GPIO_PORTD_IEV_R (*((reg32_t *)0x4000740C))
00146 #define GPIO_PORTD_IM_R (*((reg32_t *)0x40007410))
00147 #define GPIO_PORTD_RIS_R (*((reg32_t *)0x40007414))
00148 #define GPIO_PORTD_MIS_R (*((reg32_t *)0x40007418))
00149 #define GPIO_PORTD_ICR_R (*((reg32_t *)0x4000741C))
00150 #define GPIO_PORTD_AFSEL_R (*((reg32_t *)0x40007420))
00151 #define GPIO_PORTD_DR2R_R (*((reg32_t *)0x40007500))
00152 #define GPIO_PORTD_DR4R_R (*((reg32_t *)0x40007504))
00153 #define GPIO_PORTD_DR8R_R (*((reg32_t *)0x40007508))
00154 #define GPIO_PORTD_ODR_R (*((reg32_t *)0x4000750C))
00155 #define GPIO_PORTD_PUR_R (*((reg32_t *)0x40007510))
00156 #define GPIO_PORTD_PDR_R (*((reg32_t *)0x40007514))
00157 #define GPIO_PORTD_SLR_R (*((reg32_t *)0x40007518))
00158 #define GPIO_PORTD_DEN_R (*((reg32_t *)0x4000751C))
00159 #define GPIO_PORTD_LOCK_R (*((reg32_t *)0x40007520))
00160 #define GPIO_PORTD_CR_R (*((reg32_t *)0x40007524))
00161
00162
00166
00167 #define SSI0_CR0_R (*((reg32_t *)0x40008000))
00168 #define SSI0_CR1_R (*((reg32_t *)0x40008004))
00169 #define SSI0_DR_R (*((reg32_t *)0x40008008))
00170 #define SSI0_SR_R (*((reg32_t *)0x4000800C))
00171 #define SSI0_CPSR_R (*((reg32_t *)0x40008010))
00172 #define SSI0_IM_R (*((reg32_t *)0x40008014))
00173 #define SSI0_RIS_R (*((reg32_t *)0x40008018))
00174 #define SSI0_MIS_R (*((reg32_t *)0x4000801C))
00175 #define SSI0_ICR_R (*((reg32_t *)0x40008020))
00176
00177
00181
00182 #define SSI1_CR0_R (*((reg32_t *)0x40009000))
00183 #define SSI1_CR1_R (*((reg32_t *)0x40009004))
00184 #define SSI1_DR_R (*((reg32_t *)0x40009008))
00185 #define SSI1_SR_R (*((reg32_t *)0x4000900C))
00186 #define SSI1_CPSR_R (*((reg32_t *)0x40009010))
00187 #define SSI1_IM_R (*((reg32_t *)0x40009014))
00188 #define SSI1_RIS_R (*((reg32_t *)0x40009018))
00189 #define SSI1_MIS_R (*((reg32_t *)0x4000901C))
00190 #define SSI1_ICR_R (*((reg32_t *)0x40009020))
00191
00192
00196
00197 #define UART0_DR_R (*((reg32_t *)0x4000C000))
00198 #define UART0_RSR_R (*((reg32_t *)0x4000C004))
00199 #define UART0_ECR_R (*((reg32_t *)0x4000C004))
00200 #define UART0_FR_R (*((reg32_t *)0x4000C018))
00201 #define UART0_ILPR_R (*((reg32_t *)0x4000C020))
00202 #define UART0_IBRD_R (*((reg32_t *)0x4000C024))
00203 #define UART0_FBRD_R (*((reg32_t *)0x4000C028))
00204 #define UART0_LCRH_R (*((reg32_t *)0x4000C02C))
00205 #define UART0_CTL_R (*((reg32_t *)0x4000C030))
00206 #define UART0_IFLS_R (*((reg32_t *)0x4000C034))
00207 #define UART0_IM_R (*((reg32_t *)0x4000C038))
00208 #define UART0_RIS_R (*((reg32_t *)0x4000C03C))
00209 #define UART0_MIS_R (*((reg32_t *)0x4000C040))
00210 #define UART0_ICR_R (*((reg32_t *)0x4000C044))
00211
00212
00216
00217 #define UART1_DR_R (*((reg32_t *)0x4000D000))
00218 #define UART1_RSR_R (*((reg32_t *)0x4000D004))
00219 #define UART1_ECR_R (*((reg32_t *)0x4000D004))
00220 #define UART1_FR_R (*((reg32_t *)0x4000D018))
00221 #define UART1_ILPR_R (*((reg32_t *)0x4000D020))
00222 #define UART1_IBRD_R (*((reg32_t *)0x4000D024))
00223 #define UART1_FBRD_R (*((reg32_t *)0x4000D028))
00224 #define UART1_LCRH_R (*((reg32_t *)0x4000D02C))
00225 #define UART1_CTL_R (*((reg32_t *)0x4000D030))
00226 #define UART1_IFLS_R (*((reg32_t *)0x4000D034))
00227 #define UART1_IM_R (*((reg32_t *)0x4000D038))
00228 #define UART1_RIS_R (*((reg32_t *)0x4000D03C))
00229 #define UART1_MIS_R (*((reg32_t *)0x4000D040))
00230 #define UART1_ICR_R (*((reg32_t *)0x4000D044))
00231
00232
00236
00237 #define UART2_DR_R (*((reg32_t *)0x4000E000))
00238 #define UART2_RSR_R (*((reg32_t *)0x4000E004))
00239 #define UART2_ECR_R (*((reg32_t *)0x4000E004))
00240 #define UART2_FR_R (*((reg32_t *)0x4000E018))
00241 #define UART2_ILPR_R (*((reg32_t *)0x4000E020))
00242 #define UART2_IBRD_R (*((reg32_t *)0x4000E024))
00243 #define UART2_FBRD_R (*((reg32_t *)0x4000E028))
00244 #define UART2_LCRH_R (*((reg32_t *)0x4000E02C))
00245 #define UART2_CTL_R (*((reg32_t *)0x4000E030))
00246 #define UART2_IFLS_R (*((reg32_t *)0x4000E034))
00247 #define UART2_IM_R (*((reg32_t *)0x4000E038))
00248 #define UART2_RIS_R (*((reg32_t *)0x4000E03C))
00249 #define UART2_MIS_R (*((reg32_t *)0x4000E040))
00250 #define UART2_ICR_R (*((reg32_t *)0x4000E044))
00251
00252
00256
00257 #define I2C0_MASTER_MSA_R (*((reg32_t *)0x40020000))
00258 #define I2C0_MASTER_SOAR_R (*((reg32_t *)0x40020000))
00259 #define I2C0_MASTER_SCSR_R (*((reg32_t *)0x40020004))
00260 #define I2C0_MASTER_MCS_R (*((reg32_t *)0x40020004))
00261 #define I2C0_MASTER_SDR_R (*((reg32_t *)0x40020008))
00262 #define I2C0_MASTER_MDR_R (*((reg32_t *)0x40020008))
00263 #define I2C0_MASTER_MTPR_R (*((reg32_t *)0x4002000C))
00264 #define I2C0_MASTER_SIMR_R (*((reg32_t *)0x4002000C))
00265 #define I2C0_MASTER_SRIS_R (*((reg32_t *)0x40020010))
00266 #define I2C0_MASTER_MIMR_R (*((reg32_t *)0x40020010))
00267 #define I2C0_MASTER_MRIS_R (*((reg32_t *)0x40020014))
00268 #define I2C0_MASTER_SMIS_R (*((reg32_t *)0x40020014))
00269 #define I2C0_MASTER_SICR_R (*((reg32_t *)0x40020018))
00270 #define I2C0_MASTER_MMIS_R (*((reg32_t *)0x40020018))
00271 #define I2C0_MASTER_MICR_R (*((reg32_t *)0x4002001C))
00272 #define I2C0_MASTER_MCR_R (*((reg32_t *)0x40020020))
00273
00274
00278
00279 #define I2C0_SLAVE_MSA_R (*((reg32_t *)0x40020800))
00280 #define I2C0_SLAVE_SOAR_R (*((reg32_t *)0x40020800))
00281 #define I2C0_SLAVE_SCSR_R (*((reg32_t *)0x40020804))
00282 #define I2C0_SLAVE_MCS_R (*((reg32_t *)0x40020804))
00283 #define I2C0_SLAVE_SDR_R (*((reg32_t *)0x40020808))
00284 #define I2C0_SLAVE_MDR_R (*((reg32_t *)0x40020808))
00285 #define I2C0_SLAVE_MTPR_R (*((reg32_t *)0x4002080C))
00286 #define I2C0_SLAVE_SIMR_R (*((reg32_t *)0x4002080C))
00287 #define I2C0_SLAVE_SRIS_R (*((reg32_t *)0x40020810))
00288 #define I2C0_SLAVE_MIMR_R (*((reg32_t *)0x40020810))
00289 #define I2C0_SLAVE_MRIS_R (*((reg32_t *)0x40020814))
00290 #define I2C0_SLAVE_SMIS_R (*((reg32_t *)0x40020814))
00291 #define I2C0_SLAVE_SICR_R (*((reg32_t *)0x40020818))
00292 #define I2C0_SLAVE_MMIS_R (*((reg32_t *)0x40020818))
00293 #define I2C0_SLAVE_MICR_R (*((reg32_t *)0x4002081C))
00294 #define I2C0_SLAVE_MCR_R (*((reg32_t *)0x40020820))
00295
00296
00300
00301 #define I2C1_MASTER_MSA_R (*((reg32_t *)0x40021000))
00302 #define I2C1_MASTER_SOAR_R (*((reg32_t *)0x40021000))
00303 #define I2C1_MASTER_SCSR_R (*((reg32_t *)0x40021004))
00304 #define I2C1_MASTER_MCS_R (*((reg32_t *)0x40021004))
00305 #define I2C1_MASTER_SDR_R (*((reg32_t *)0x40021008))
00306 #define I2C1_MASTER_MDR_R (*((reg32_t *)0x40021008))
00307 #define I2C1_MASTER_MTPR_R (*((reg32_t *)0x4002100C))
00308 #define I2C1_MASTER_SIMR_R (*((reg32_t *)0x4002100C))
00309 #define I2C1_MASTER_SRIS_R (*((reg32_t *)0x40021010))
00310 #define I2C1_MASTER_MIMR_R (*((reg32_t *)0x40021010))
00311 #define I2C1_MASTER_MRIS_R (*((reg32_t *)0x40021014))
00312 #define I2C1_MASTER_SMIS_R (*((reg32_t *)0x40021014))
00313 #define I2C1_MASTER_SICR_R (*((reg32_t *)0x40021018))
00314 #define I2C1_MASTER_MMIS_R (*((reg32_t *)0x40021018))
00315 #define I2C1_MASTER_MICR_R (*((reg32_t *)0x4002101C))
00316 #define I2C1_MASTER_MCR_R (*((reg32_t *)0x40021020))
00317
00318
00322
00323 #define I2C1_SLAVE_MSA_R (*((reg32_t *)0x40021800))
00324 #define I2C1_SLAVE_SOAR_R (*((reg32_t *)0x40021800))
00325 #define I2C1_SLAVE_SCSR_R (*((reg32_t *)0x40021804))
00326 #define I2C1_SLAVE_MCS_R (*((reg32_t *)0x40021804))
00327 #define I2C1_SLAVE_SDR_R (*((reg32_t *)0x40021808))
00328 #define I2C1_SLAVE_MDR_R (*((reg32_t *)0x40021808))
00329 #define I2C1_SLAVE_MTPR_R (*((reg32_t *)0x4002180C))
00330 #define I2C1_SLAVE_SIMR_R (*((reg32_t *)0x4002180C))
00331 #define I2C1_SLAVE_SRIS_R (*((reg32_t *)0x40021810))
00332 #define I2C1_SLAVE_MIMR_R (*((reg32_t *)0x40021810))
00333 #define I2C1_SLAVE_MRIS_R (*((reg32_t *)0x40021814))
00334 #define I2C1_SLAVE_SMIS_R (*((reg32_t *)0x40021814))
00335 #define I2C1_SLAVE_SICR_R (*((reg32_t *)0x40021818))
00336 #define I2C1_SLAVE_MMIS_R (*((reg32_t *)0x40021818))
00337 #define I2C1_SLAVE_MICR_R (*((reg32_t *)0x4002181C))
00338 #define I2C1_SLAVE_MCR_R (*((reg32_t *)0x40021820))
00339
00340
00344
00345 #define GPIO_PORTE_DATA_BITS_R ((reg32_t *)0x40024000)
00346 #define GPIO_PORTE_DATA_R (*((reg32_t *)0x400243FC))
00347 #define GPIO_PORTE_DIR_R (*((reg32_t *)0x40024400))
00348 #define GPIO_PORTE_IS_R (*((reg32_t *)0x40024404))
00349 #define GPIO_PORTE_IBE_R (*((reg32_t *)0x40024408))
00350 #define GPIO_PORTE_IEV_R (*((reg32_t *)0x4002440C))
00351 #define GPIO_PORTE_IM_R (*((reg32_t *)0x40024410))
00352 #define GPIO_PORTE_RIS_R (*((reg32_t *)0x40024414))
00353 #define GPIO_PORTE_MIS_R (*((reg32_t *)0x40024418))
00354 #define GPIO_PORTE_ICR_R (*((reg32_t *)0x4002441C))
00355 #define GPIO_PORTE_AFSEL_R (*((reg32_t *)0x40024420))
00356 #define GPIO_PORTE_DR2R_R (*((reg32_t *)0x40024500))
00357 #define GPIO_PORTE_DR4R_R (*((reg32_t *)0x40024504))
00358 #define GPIO_PORTE_DR8R_R (*((reg32_t *)0x40024508))
00359 #define GPIO_PORTE_ODR_R (*((reg32_t *)0x4002450C))
00360 #define GPIO_PORTE_PUR_R (*((reg32_t *)0x40024510))
00361 #define GPIO_PORTE_PDR_R (*((reg32_t *)0x40024514))
00362 #define GPIO_PORTE_SLR_R (*((reg32_t *)0x40024518))
00363 #define GPIO_PORTE_DEN_R (*((reg32_t *)0x4002451C))
00364 #define GPIO_PORTE_LOCK_R (*((reg32_t *)0x40024520))
00365 #define GPIO_PORTE_CR_R (*((reg32_t *)0x40024524))
00366
00367
00371
00372 #define GPIO_PORTF_DATA_BITS_R ((reg32_t *)0x40025000)
00373 #define GPIO_PORTF_DATA_R (*((reg32_t *)0x400253FC))
00374 #define GPIO_PORTF_DIR_R (*((reg32_t *)0x40025400))
00375 #define GPIO_PORTF_IS_R (*((reg32_t *)0x40025404))
00376 #define GPIO_PORTF_IBE_R (*((reg32_t *)0x40025408))
00377 #define GPIO_PORTF_IEV_R (*((reg32_t *)0x4002540C))
00378 #define GPIO_PORTF_IM_R (*((reg32_t *)0x40025410))
00379 #define GPIO_PORTF_RIS_R (*((reg32_t *)0x40025414))
00380 #define GPIO_PORTF_MIS_R (*((reg32_t *)0x40025418))
00381 #define GPIO_PORTF_ICR_R (*((reg32_t *)0x4002541C))
00382 #define GPIO_PORTF_AFSEL_R (*((reg32_t *)0x40025420))
00383 #define GPIO_PORTF_DR2R_R (*((reg32_t *)0x40025500))
00384 #define GPIO_PORTF_DR4R_R (*((reg32_t *)0x40025504))
00385 #define GPIO_PORTF_DR8R_R (*((reg32_t *)0x40025508))
00386 #define GPIO_PORTF_ODR_R (*((reg32_t *)0x4002550C))
00387 #define GPIO_PORTF_PUR_R (*((reg32_t *)0x40025510))
00388 #define GPIO_PORTF_PDR_R (*((reg32_t *)0x40025514))
00389 #define GPIO_PORTF_SLR_R (*((reg32_t *)0x40025518))
00390 #define GPIO_PORTF_DEN_R (*((reg32_t *)0x4002551C))
00391 #define GPIO_PORTF_LOCK_R (*((reg32_t *)0x40025520))
00392 #define GPIO_PORTF_CR_R (*((reg32_t *)0x40025524))
00393
00394
00398
00399 #define GPIO_PORTG_DATA_BITS_R ((reg32_t *)0x40026000)
00400 #define GPIO_PORTG_DATA_R (*((reg32_t *)0x400263FC))
00401 #define GPIO_PORTG_DIR_R (*((reg32_t *)0x40026400))
00402 #define GPIO_PORTG_IS_R (*((reg32_t *)0x40026404))
00403 #define GPIO_PORTG_IBE_R (*((reg32_t *)0x40026408))
00404 #define GPIO_PORTG_IEV_R (*((reg32_t *)0x4002640C))
00405 #define GPIO_PORTG_IM_R (*((reg32_t *)0x40026410))
00406 #define GPIO_PORTG_RIS_R (*((reg32_t *)0x40026414))
00407 #define GPIO_PORTG_MIS_R (*((reg32_t *)0x40026418))
00408 #define GPIO_PORTG_ICR_R (*((reg32_t *)0x4002641C))
00409 #define GPIO_PORTG_AFSEL_R (*((reg32_t *)0x40026420))
00410 #define GPIO_PORTG_DR2R_R (*((reg32_t *)0x40026500))
00411 #define GPIO_PORTG_DR4R_R (*((reg32_t *)0x40026504))
00412 #define GPIO_PORTG_DR8R_R (*((reg32_t *)0x40026508))
00413 #define GPIO_PORTG_ODR_R (*((reg32_t *)0x4002650C))
00414 #define GPIO_PORTG_PUR_R (*((reg32_t *)0x40026510))
00415 #define GPIO_PORTG_PDR_R (*((reg32_t *)0x40026514))
00416 #define GPIO_PORTG_SLR_R (*((reg32_t *)0x40026518))
00417 #define GPIO_PORTG_DEN_R (*((reg32_t *)0x4002651C))
00418 #define GPIO_PORTG_LOCK_R (*((reg32_t *)0x40026520))
00419 #define GPIO_PORTG_CR_R (*((reg32_t *)0x40026524))
00420
00421
00425
00426 #define GPIO_PORTH_DATA_BITS_R ((reg32_t *)0x40027000)
00427 #define GPIO_PORTH_DATA_R (*((reg32_t *)0x400273FC))
00428 #define GPIO_PORTH_DIR_R (*((reg32_t *)0x40027400))
00429 #define GPIO_PORTH_IS_R (*((reg32_t *)0x40027404))
00430 #define GPIO_PORTH_IBE_R (*((reg32_t *)0x40027408))
00431 #define GPIO_PORTH_IEV_R (*((reg32_t *)0x4002740C))
00432 #define GPIO_PORTH_IM_R (*((reg32_t *)0x40027410))
00433 #define GPIO_PORTH_RIS_R (*((reg32_t *)0x40027414))
00434 #define GPIO_PORTH_MIS_R (*((reg32_t *)0x40027418))
00435 #define GPIO_PORTH_ICR_R (*((reg32_t *)0x4002741C))
00436 #define GPIO_PORTH_AFSEL_R (*((reg32_t *)0x40027420))
00437 #define GPIO_PORTH_DR2R_R (*((reg32_t *)0x40027500))
00438 #define GPIO_PORTH_DR4R_R (*((reg32_t *)0x40027504))
00439 #define GPIO_PORTH_DR8R_R (*((reg32_t *)0x40027508))
00440 #define GPIO_PORTH_ODR_R (*((reg32_t *)0x4002750C))
00441 #define GPIO_PORTH_PUR_R (*((reg32_t *)0x40027510))
00442 #define GPIO_PORTH_PDR_R (*((reg32_t *)0x40027514))
00443 #define GPIO_PORTH_SLR_R (*((reg32_t *)0x40027518))
00444 #define GPIO_PORTH_DEN_R (*((reg32_t *)0x4002751C))
00445 #define GPIO_PORTH_LOCK_R (*((reg32_t *)0x40027520))
00446 #define GPIO_PORTH_CR_R (*((reg32_t *)0x40027524))
00447
00448
00452
00453 #define PWM_CTL_R (*((reg32_t *)0x40028000))
00454 #define PWM_SYNC_R (*((reg32_t *)0x40028004))
00455 #define PWM_ENABLE_R (*((reg32_t *)0x40028008))
00456 #define PWM_INVERT_R (*((reg32_t *)0x4002800C))
00457 #define PWM_FAULT_R (*((reg32_t *)0x40028010))
00458 #define PWM_INTEN_R (*((reg32_t *)0x40028014))
00459 #define PWM_RIS_R (*((reg32_t *)0x40028018))
00460 #define PWM_ISC_R (*((reg32_t *)0x4002801C))
00461 #define PWM_STATUS_R (*((reg32_t *)0x40028020))
00462 #define PWM_0_CTL_R (*((reg32_t *)0x40028040))
00463 #define PWM_0_INTEN_R (*((reg32_t *)0x40028044))
00464 #define PWM_0_RIS_R (*((reg32_t *)0x40028048))
00465 #define PWM_0_ISC_R (*((reg32_t *)0x4002804C))
00466 #define PWM_0_LOAD_R (*((reg32_t *)0x40028050))
00467 #define PWM_0_COUNT_R (*((reg32_t *)0x40028054))
00468 #define PWM_0_CMPA_R (*((reg32_t *)0x40028058))
00469 #define PWM_0_CMPB_R (*((reg32_t *)0x4002805C))
00470 #define PWM_0_GENA_R (*((reg32_t *)0x40028060))
00471 #define PWM_0_GENB_R (*((reg32_t *)0x40028064))
00472 #define PWM_0_DBCTL_R (*((reg32_t *)0x40028068))
00473 #define PWM_0_DBRISE_R (*((reg32_t *)0x4002806C))
00474 #define PWM_0_DBFALL_R (*((reg32_t *)0x40028070))
00475 #define PWM_1_CTL_R (*((reg32_t *)0x40028080))
00476 #define PWM_1_INTEN_R (*((reg32_t *)0x40028084))
00477 #define PWM_1_RIS_R (*((reg32_t *)0x40028088))
00478 #define PWM_1_ISC_R (*((reg32_t *)0x4002808C))
00479 #define PWM_1_LOAD_R (*((reg32_t *)0x40028090))
00480 #define PWM_1_COUNT_R (*((reg32_t *)0x40028094))
00481 #define PWM_1_CMPA_R (*((reg32_t *)0x40028098))
00482 #define PWM_1_CMPB_R (*((reg32_t *)0x4002809C))
00483 #define PWM_1_GENA_R (*((reg32_t *)0x400280A0))
00484 #define PWM_1_GENB_R (*((reg32_t *)0x400280A4))
00485 #define PWM_1_DBCTL_R (*((reg32_t *)0x400280A8))
00486 #define PWM_1_DBRISE_R (*((reg32_t *)0x400280AC))
00487 #define PWM_1_DBFALL_R (*((reg32_t *)0x400280B0))
00488 #define PWM_2_CTL_R (*((reg32_t *)0x400280C0))
00489 #define PWM_2_INTEN_R (*((reg32_t *)0x400280C4))
00490 #define PWM_2_RIS_R (*((reg32_t *)0x400280C8))
00491 #define PWM_2_ISC_R (*((reg32_t *)0x400280CC))
00492 #define PWM_2_LOAD_R (*((reg32_t *)0x400280D0))
00493 #define PWM_2_COUNT_R (*((reg32_t *)0x400280D4))
00494 #define PWM_2_CMPA_R (*((reg32_t *)0x400280D8))
00495 #define PWM_2_CMPB_R (*((reg32_t *)0x400280DC))
00496 #define PWM_2_GENA_R (*((reg32_t *)0x400280E0))
00497 #define PWM_2_GENB_R (*((reg32_t *)0x400280E4))
00498 #define PWM_2_DBCTL_R (*((reg32_t *)0x400280E8))
00499 #define PWM_2_DBRISE_R (*((reg32_t *)0x400280EC))
00500 #define PWM_2_DBFALL_R (*((reg32_t *)0x400280F0))
00501
00502
00506
00507 #define QEI0_CTL_R (*((reg32_t *)0x4002C000))
00508 #define QEI0_STAT_R (*((reg32_t *)0x4002C004))
00509 #define QEI0_POS_R (*((reg32_t *)0x4002C008))
00510 #define QEI0_MAXPOS_R (*((reg32_t *)0x4002C00C))
00511 #define QEI0_LOAD_R (*((reg32_t *)0x4002C010))
00512 #define QEI0_TIME_R (*((reg32_t *)0x4002C014))
00513 #define QEI0_COUNT_R (*((reg32_t *)0x4002C018))
00514 #define QEI0_SPEED_R (*((reg32_t *)0x4002C01C))
00515 #define QEI0_INTEN_R (*((reg32_t *)0x4002C020))
00516 #define QEI0_RIS_R (*((reg32_t *)0x4002C024))
00517 #define QEI0_ISC_R (*((reg32_t *)0x4002C028))
00518
00519
00523
00524 #define QEI1_CTL_R (*((reg32_t *)0x4002D000))
00525 #define QEI1_STAT_R (*((reg32_t *)0x4002D004))
00526 #define QEI1_POS_R (*((reg32_t *)0x4002D008))
00527 #define QEI1_MAXPOS_R (*((reg32_t *)0x4002D00C))
00528 #define QEI1_LOAD_R (*((reg32_t *)0x4002D010))
00529 #define QEI1_TIME_R (*((reg32_t *)0x4002D014))
00530 #define QEI1_COUNT_R (*((reg32_t *)0x4002D018))
00531 #define QEI1_SPEED_R (*((reg32_t *)0x4002D01C))
00532 #define QEI1_INTEN_R (*((reg32_t *)0x4002D020))
00533 #define QEI1_RIS_R (*((reg32_t *)0x4002D024))
00534 #define QEI1_ISC_R (*((reg32_t *)0x4002D028))
00535
00536
00540
00541 #define TIMER0_CFG_R (*((reg32_t *)0x40030000))
00542 #define TIMER0_TAMR_R (*((reg32_t *)0x40030004))
00543 #define TIMER0_TBMR_R (*((reg32_t *)0x40030008))
00544 #define TIMER0_CTL_R (*((reg32_t *)0x4003000C))
00545 #define TIMER0_IMR_R (*((reg32_t *)0x40030018))
00546 #define TIMER0_RIS_R (*((reg32_t *)0x4003001C))
00547 #define TIMER0_MIS_R (*((reg32_t *)0x40030020))
00548 #define TIMER0_ICR_R (*((reg32_t *)0x40030024))
00549 #define TIMER0_TAILR_R (*((reg32_t *)0x40030028))
00550 #define TIMER0_TBILR_R (*((reg32_t *)0x4003002C))
00551 #define TIMER0_TAMATCHR_R (*((reg32_t *)0x40030030))
00552 #define TIMER0_TBMATCHR_R (*((reg32_t *)0x40030034))
00553 #define TIMER0_TAPR_R (*((reg32_t *)0x40030038))
00554 #define TIMER0_TBPR_R (*((reg32_t *)0x4003003C))
00555 #define TIMER0_TAPMR_R (*((reg32_t *)0x40030040))
00556 #define TIMER0_TBPMR_R (*((reg32_t *)0x40030044))
00557 #define TIMER0_TAR_R (*((reg32_t *)0x40030048))
00558 #define TIMER0_TBR_R (*((reg32_t *)0x4003004C))
00559
00560
00564
00565 #define TIMER1_CFG_R (*((reg32_t *)0x40031000))
00566 #define TIMER1_TAMR_R (*((reg32_t *)0x40031004))
00567 #define TIMER1_TBMR_R (*((reg32_t *)0x40031008))
00568 #define TIMER1_CTL_R (*((reg32_t *)0x4003100C))
00569 #define TIMER1_IMR_R (*((reg32_t *)0x40031018))
00570 #define TIMER1_RIS_R (*((reg32_t *)0x4003101C))
00571 #define TIMER1_MIS_R (*((reg32_t *)0x40031020))
00572 #define TIMER1_ICR_R (*((reg32_t *)0x40031024))
00573 #define TIMER1_TAILR_R (*((reg32_t *)0x40031028))
00574 #define TIMER1_TBILR_R (*((reg32_t *)0x4003102C))
00575 #define TIMER1_TAMATCHR_R (*((reg32_t *)0x40031030))
00576 #define TIMER1_TBMATCHR_R (*((reg32_t *)0x40031034))
00577 #define TIMER1_TAPR_R (*((reg32_t *)0x40031038))
00578 #define TIMER1_TBPR_R (*((reg32_t *)0x4003103C))
00579 #define TIMER1_TAPMR_R (*((reg32_t *)0x40031040))
00580 #define TIMER1_TBPMR_R (*((reg32_t *)0x40031044))
00581 #define TIMER1_TAR_R (*((reg32_t *)0x40031048))
00582 #define TIMER1_TBR_R (*((reg32_t *)0x4003104C))
00583
00584
00588
00589 #define TIMER2_CFG_R (*((reg32_t *)0x40032000))
00590 #define TIMER2_TAMR_R (*((reg32_t *)0x40032004))
00591 #define TIMER2_TBMR_R (*((reg32_t *)0x40032008))
00592 #define TIMER2_CTL_R (*((reg32_t *)0x4003200C))
00593 #define TIMER2_IMR_R (*((reg32_t *)0x40032018))
00594 #define TIMER2_RIS_R (*((reg32_t *)0x4003201C))
00595 #define TIMER2_MIS_R (*((reg32_t *)0x40032020))
00596 #define TIMER2_ICR_R (*((reg32_t *)0x40032024))
00597 #define TIMER2_TAILR_R (*((reg32_t *)0x40032028))
00598 #define TIMER2_TBILR_R (*((reg32_t *)0x4003202C))
00599 #define TIMER2_TAMATCHR_R (*((reg32_t *)0x40032030))
00600 #define TIMER2_TBMATCHR_R (*((reg32_t *)0x40032034))
00601 #define TIMER2_TAPR_R (*((reg32_t *)0x40032038))
00602 #define TIMER2_TBPR_R (*((reg32_t *)0x4003203C))
00603 #define TIMER2_TAPMR_R (*((reg32_t *)0x40032040))
00604 #define TIMER2_TBPMR_R (*((reg32_t *)0x40032044))
00605 #define TIMER2_TAR_R (*((reg32_t *)0x40032048))
00606 #define TIMER2_TBR_R (*((reg32_t *)0x4003204C))
00607
00608
00612
00613 #define TIMER3_CFG_R (*((reg32_t *)0x40033000))
00614 #define TIMER3_TAMR_R (*((reg32_t *)0x40033004))
00615 #define TIMER3_TBMR_R (*((reg32_t *)0x40033008))
00616 #define TIMER3_CTL_R (*((reg32_t *)0x4003300C))
00617 #define TIMER3_IMR_R (*((reg32_t *)0x40033018))
00618 #define TIMER3_RIS_R (*((reg32_t *)0x4003301C))
00619 #define TIMER3_MIS_R (*((reg32_t *)0x40033020))
00620 #define TIMER3_ICR_R (*((reg32_t *)0x40033024))
00621 #define TIMER3_TAILR_R (*((reg32_t *)0x40033028))
00622 #define TIMER3_TBILR_R (*((reg32_t *)0x4003302C))
00623 #define TIMER3_TAMATCHR_R (*((reg32_t *)0x40033030))
00624 #define TIMER3_TBMATCHR_R (*((reg32_t *)0x40033034))
00625 #define TIMER3_TAPR_R (*((reg32_t *)0x40033038))
00626 #define TIMER3_TBPR_R (*((reg32_t *)0x4003303C))
00627 #define TIMER3_TAPMR_R (*((reg32_t *)0x40033040))
00628 #define TIMER3_TBPMR_R (*((reg32_t *)0x40033044))
00629 #define TIMER3_TAR_R (*((reg32_t *)0x40033048))
00630 #define TIMER3_TBR_R (*((reg32_t *)0x4003304C))
00631
00632
00636
00637 #define ADC0_ACTSS_R (*((reg32_t *)0x40038000))
00638 #define ADC0_RIS_R (*((reg32_t *)0x40038004))
00639 #define ADC0_IM_R (*((reg32_t *)0x40038008))
00640 #define ADC0_ISC_R (*((reg32_t *)0x4003800C))
00641 #define ADC0_OSTAT_R (*((reg32_t *)0x40038010))
00642 #define ADC0_EMUX_R (*((reg32_t *)0x40038014))
00643 #define ADC0_USTAT_R (*((reg32_t *)0x40038018))
00644 #define ADC0_SSPRI_R (*((reg32_t *)0x40038020))
00645 #define ADC0_PSSI_R (*((reg32_t *)0x40038028))
00646 #define ADC0_SAC_R (*((reg32_t *)0x40038030))
00647 #define ADC0_SSMUX0_R (*((reg32_t *)0x40038040))
00648 #define ADC0_SSCTL0_R (*((reg32_t *)0x40038044))
00649 #define ADC0_SSFIFO0_R (*((reg32_t *)0x40038048))
00650 #define ADC0_SSFSTAT0_R (*((reg32_t *)0x4003804C))
00651 #define ADC0_SSMUX1_R (*((reg32_t *)0x40038060))
00652 #define ADC0_SSCTL1_R (*((reg32_t *)0x40038064))
00653 #define ADC0_SSFIFO1_R (*((reg32_t *)0x40038068))
00654 #define ADC0_SSFSTAT1_R (*((reg32_t *)0x4003806C))
00655 #define ADC0_SSMUX2_R (*((reg32_t *)0x40038080))
00656 #define ADC0_SSCTL2_R (*((reg32_t *)0x40038084))
00657 #define ADC0_SSFIFO2_R (*((reg32_t *)0x40038088))
00658 #define ADC0_SSFSTAT2_R (*((reg32_t *)0x4003808C))
00659 #define ADC0_SSMUX3_R (*((reg32_t *)0x400380A0))
00660 #define ADC0_SSCTL3_R (*((reg32_t *)0x400380A4))
00661 #define ADC0_SSFIFO3_R (*((reg32_t *)0x400380A8))
00662 #define ADC0_SSFSTAT3_R (*((reg32_t *)0x400380AC))
00663 #define ADC0_TMLB_R (*((reg32_t *)0x40038100))
00664
00665
00669
00670 #define COMP_ACMIS_R (*((reg32_t *)0x4003C000))
00671 #define COMP_ACRIS_R (*((reg32_t *)0x4003C004))
00672 #define COMP_ACINTEN_R (*((reg32_t *)0x4003C008))
00673 #define COMP_ACREFCTL_R (*((reg32_t *)0x4003C010))
00674 #define COMP_ACSTAT0_R (*((reg32_t *)0x4003C020))
00675 #define COMP_ACCTL0_R (*((reg32_t *)0x4003C024))
00676 #define COMP_ACSTAT1_R (*((reg32_t *)0x4003C040))
00677 #define COMP_ACCTL1_R (*((reg32_t *)0x4003C044))
00678 #define COMP_ACSTAT2_R (*((reg32_t *)0x4003C060))
00679 #define COMP_ACCTL2_R (*((reg32_t *)0x4003C064))
00680
00681
00685
00686 #define HIB_RTCC_R (*((reg32_t *)0x400FC000))
00687 #define HIB_RTCM0_R (*((reg32_t *)0x400FC004))
00688 #define HIB_RTCM1_R (*((reg32_t *)0x400FC008))
00689 #define HIB_RTCLD_R (*((reg32_t *)0x400FC00C))
00690 #define HIB_CTL_R (*((reg32_t *)0x400FC010))
00691 #define HIB_IM_R (*((reg32_t *)0x400FC014))
00692 #define HIB_RIS_R (*((reg32_t *)0x400FC018))
00693 #define HIB_MIS_R (*((reg32_t *)0x400FC01C))
00694 #define HIB_IC_R (*((reg32_t *)0x400FC020))
00695 #define HIB_RTCT_R (*((reg32_t *)0x400FC024))
00696 #define HIB_DATA_R (*((reg32_t *)0x400FC030))
00697
00698
00702
00703 #define FLASH_FMA_R (*((reg32_t *)0x400FD000))
00704 #define FLASH_FMD_R (*((reg32_t *)0x400FD004))
00705 #define FLASH_FMC_R (*((reg32_t *)0x400FD008))
00706 #define FLASH_FCRIS_R (*((reg32_t *)0x400FD00C))
00707 #define FLASH_FCIM_R (*((reg32_t *)0x400FD010))
00708 #define FLASH_FCMISC_R (*((reg32_t *)0x400FD014))
00709 #define FLASH_USECRL_R (*((reg32_t *)0x400FE140))
00710 #define FLASH_USERDBG_R (*((reg32_t *)0x400FE1D0))
00711 #define FLASH_USERREG0_R (*((reg32_t *)0x400FE1E0))
00712 #define FLASH_USERREG1_R (*((reg32_t *)0x400FE1E4))
00713 #define FLASH_FMPRE0_R (*((reg32_t *)0x400FE200))
00714 #define FLASH_FMPRE1_R (*((reg32_t *)0x400FE204))
00715 #define FLASH_FMPRE2_R (*((reg32_t *)0x400FE208))
00716 #define FLASH_FMPRE3_R (*((reg32_t *)0x400FE20C))
00717 #define FLASH_FMPPE0_R (*((reg32_t *)0x400FE400))
00718 #define FLASH_FMPPE1_R (*((reg32_t *)0x400FE404))
00719 #define FLASH_FMPPE2_R (*((reg32_t *)0x400FE408))
00720 #define FLASH_FMPPE3_R (*((reg32_t *)0x400FE40C))
00721
00722
00726
00727 #define SYSCTL_DID0_R (*((reg32_t *)0x400FE000))
00728 #define SYSCTL_DID1_R (*((reg32_t *)0x400FE004))
00729 #define SYSCTL_DC0_R (*((reg32_t *)0x400FE008))
00730 #define SYSCTL_DC1_R (*((reg32_t *)0x400FE010))
00731 #define SYSCTL_DC2_R (*((reg32_t *)0x400FE014))
00732 #define SYSCTL_DC3_R (*((reg32_t *)0x400FE018))
00733 #define SYSCTL_DC4_R (*((reg32_t *)0x400FE01C))
00734 #define SYSCTL_PBORCTL_R (*((reg32_t *)0x400FE030))
00735 #define SYSCTL_LDOPCTL_R (*((reg32_t *)0x400FE034))
00736 #define SYSCTL_SRCR0_R (*((reg32_t *)0x400FE040))
00737 #define SYSCTL_SRCR1_R (*((reg32_t *)0x400FE044))
00738 #define SYSCTL_SRCR2_R (*((reg32_t *)0x400FE048))
00739 #define SYSCTL_RIS_R (*((reg32_t *)0x400FE050))
00740 #define SYSCTL_IMC_R (*((reg32_t *)0x400FE054))
00741 #define SYSCTL_MISC_R (*((reg32_t *)0x400FE058))
00742 #define SYSCTL_RESC_R (*((reg32_t *)0x400FE05C))
00743 #define SYSCTL_RCC_R (*((reg32_t *)0x400FE060))
00744 #define SYSCTL_PLLCFG_R (*((reg32_t *)0x400FE064))
00745 #define SYSCTL_RCC2_R (*((reg32_t *)0x400FE070))
00746 #define SYSCTL_RCGC0_R (*((reg32_t *)0x400FE100))
00747 #define SYSCTL_RCGC1_R (*((reg32_t *)0x400FE104))
00748 #define SYSCTL_RCGC2_R (*((reg32_t *)0x400FE108))
00749 #define SYSCTL_SCGC0_R (*((reg32_t *)0x400FE110))
00750 #define SYSCTL_SCGC1_R (*((reg32_t *)0x400FE114))
00751 #define SYSCTL_SCGC2_R (*((reg32_t *)0x400FE118))
00752 #define SYSCTL_DCGC0_R (*((reg32_t *)0x400FE120))
00753 #define SYSCTL_DCGC1_R (*((reg32_t *)0x400FE124))
00754 #define SYSCTL_DCGC2_R (*((reg32_t *)0x400FE128))
00755 #define SYSCTL_DSLPCLKCFG_R (*((reg32_t *)0x400FE144))
00756
00757
00761
00762 #define NVIC_INT_TYPE_R (*((reg32_t *)0xE000E004))
00763 #define NVIC_ST_CTRL_R (*((reg32_t *)0xE000E010))
00764 #define NVIC_ST_RELOAD_R (*((reg32_t *)0xE000E014))
00765 #define NVIC_ST_CURRENT_R (*((reg32_t *)0xE000E018))
00766 #define NVIC_ST_CAL_R (*((reg32_t *)0xE000E01C))
00767 #define NVIC_EN0_R (*((reg32_t *)0xE000E100))
00768 #define NVIC_EN1_R (*((reg32_t *)0xE000E104))
00769 #define NVIC_DIS0_R (*((reg32_t *)0xE000E180))
00770 #define NVIC_DIS1_R (*((reg32_t *)0xE000E184))
00771 #define NVIC_PEND0_R (*((reg32_t *)0xE000E200))
00772 #define NVIC_PEND1_R (*((reg32_t *)0xE000E204))
00773 #define NVIC_UNPEND0_R (*((reg32_t *)0xE000E280))
00774 #define NVIC_UNPEND1_R (*((reg32_t *)0xE000E284))
00775 #define NVIC_ACTIVE0_R (*((reg32_t *)0xE000E300))
00776 #define NVIC_ACTIVE1_R (*((reg32_t *)0xE000E304))
00777 #define NVIC_PRI0_R (*((reg32_t *)0xE000E400))
00778 #define NVIC_PRI1_R (*((reg32_t *)0xE000E404))
00779 #define NVIC_PRI2_R (*((reg32_t *)0xE000E408))
00780 #define NVIC_PRI3_R (*((reg32_t *)0xE000E40C))
00781 #define NVIC_PRI4_R (*((reg32_t *)0xE000E410))
00782 #define NVIC_PRI5_R (*((reg32_t *)0xE000E414))
00783 #define NVIC_PRI6_R (*((reg32_t *)0xE000E418))
00784 #define NVIC_PRI7_R (*((reg32_t *)0xE000E41C))
00785 #define NVIC_PRI8_R (*((reg32_t *)0xE000E420))
00786 #define NVIC_PRI9_R (*((reg32_t *)0xE000E424))
00787 #define NVIC_PRI10_R (*((reg32_t *)0xE000E428))
00788 #define NVIC_CPUID_R (*((reg32_t *)0xE000ED00))
00789 #define NVIC_INT_CTRL_R (*((reg32_t *)0xE000ED04))
00790 #define NVIC_VTABLE_R (*((reg32_t *)0xE000ED08))
00791 #define NVIC_APINT_R (*((reg32_t *)0xE000ED0C))
00792 #define NVIC_SYS_CTRL_R (*((reg32_t *)0xE000ED10))
00793 #define NVIC_CFG_CTRL_R (*((reg32_t *)0xE000ED14))
00794 #define NVIC_SYS_PRI1_R (*((reg32_t *)0xE000ED18))
00795 #define NVIC_SYS_PRI2_R (*((reg32_t *)0xE000ED1C))
00796 #define NVIC_SYS_PRI3_R (*((reg32_t *)0xE000ED20))
00797 #define NVIC_SYS_HND_CTRL_R (*((reg32_t *)0xE000ED24))
00798 #define NVIC_FAULT_STAT_R (*((reg32_t *)0xE000ED28))
00799 #define NVIC_HFAULT_STAT_R (*((reg32_t *)0xE000ED2C))
00800 #define NVIC_DEBUG_STAT_R (*((reg32_t *)0xE000ED30))
00801 #define NVIC_MM_ADDR_R (*((reg32_t *)0xE000ED34))
00802 #define NVIC_FAULT_ADDR_R (*((reg32_t *)0xE000ED38))
00803 #define NVIC_MPU_TYPE_R (*((reg32_t *)0xE000ED90))
00804 #define NVIC_MPU_CTRL_R (*((reg32_t *)0xE000ED94))
00805 #define NVIC_MPU_NUMBER_R (*((reg32_t *)0xE000ED98))
00806 #define NVIC_MPU_BASE_R (*((reg32_t *)0xE000ED9C))
00807 #define NVIC_MPU_ATTR_R (*((reg32_t *)0xE000EDA0))
00808 #define NVIC_DBG_CTRL_R (*((reg32_t *)0xE000EDF0))
00809 #define NVIC_DBG_XFER_R (*((reg32_t *)0xE000EDF4))
00810 #define NVIC_DBG_DATA_R (*((reg32_t *)0xE000EDF8))
00811 #define NVIC_DBG_INT_R (*((reg32_t *)0xE000EDFC))
00812 #define NVIC_SW_TRIG_R (*((reg32_t *)0xE000EF00))
00813
00814
00818
00819 #define WDT_LOAD_M 0xFFFFFFFF ///< Watchdog Load Value
00820 #define WDT_LOAD_S 0
00821
00822
00826
00827 #define WDT_VALUE_M 0xFFFFFFFF ///< Watchdog Value
00828 #define WDT_VALUE_S 0
00829
00830
00834
00835 #define WDT_CTL_RESEN 0x00000002 ///< Watchdog Reset Enable
00836 #define WDT_CTL_INTEN 0x00000001 ///< Watchdog Interrupt Enable
00837
00838
00842
00843 #define WDT_ICR_M 0xFFFFFFFF ///< Watchdog Interrupt Clear
00844 #define WDT_ICR_S 0
00845
00846
00850
00851 #define WDT_RIS_WDTRIS 0x00000001 ///< Watchdog Raw Interrupt Status
00852
00853
00857
00858 #define WDT_MIS_WDTMIS 0x00000001 ///< Watchdog Masked Interrupt Status
00859
00860
00864
00865 #define WDT_TEST_STALL 0x00000100 ///< Watchdog Stall Enable
00866
00867
00871
00872 #define WDT_LOCK_M 0xFFFFFFFF ///< Watchdog Lock
00873 #define WDT_LOCK_UNLOCKED 0x00000000 ///< Unlocked
00874 #define WDT_LOCK_LOCKED 0x00000001 ///< Locked
00875 #define WDT_LOCK_UNLOCK 0x1ACCE551 ///< Unlocks the watchdog timer
00876
00877
00881
00882 #define GPIO_LOCK_M 0xFFFFFFFF ///< GPIO Lock
00883 #define GPIO_LOCK_UNLOCKED 0x00000000 ///< The GPIOCR register is unlocked
00884
00885 #define GPIO_LOCK_LOCKED 0x00000001 ///< The GPIOCR register is locked
00886
00887 #define GPIO_LOCK_KEY 0x1ACCE551 ///< Unlocks the GPIO_CR register
00888
00889
00893
00894 #define SSI_CR0_SCR_M 0x0000FF00 ///< SSI Serial Clock Rate
00895 #define SSI_CR0_SPH 0x00000080 ///< SSI Serial Clock Phase
00896 #define SSI_CR0_SPO 0x00000040 ///< SSI Serial Clock Polarity
00897 #define SSI_CR0_FRF_M 0x00000030 ///< SSI Frame Format Select
00898 #define SSI_CR0_FRF_MOTO 0x00000000 ///< Freescale SPI Frame Format
00899 #define SSI_CR0_FRF_TI 0x00000010 ///< Texas Instruments Synchronous
00900
00901 #define SSI_CR0_FRF_NMW 0x00000020 ///< MICROWIRE Frame Format
00902 #define SSI_CR0_DSS_M 0x0000000F ///< SSI Data Size Select
00903 #define SSI_CR0_DSS_4 0x00000003 ///< 4-bit data
00904 #define SSI_CR0_DSS_5 0x00000004 ///< 5-bit data
00905 #define SSI_CR0_DSS_6 0x00000005 ///< 6-bit data
00906 #define SSI_CR0_DSS_7 0x00000006 ///< 7-bit data
00907 #define SSI_CR0_DSS_8 0x00000007 ///< 8-bit data
00908 #define SSI_CR0_DSS_9 0x00000008 ///< 9-bit data
00909 #define SSI_CR0_DSS_10 0x00000009 ///< 10-bit data
00910 #define SSI_CR0_DSS_11 0x0000000A ///< 11-bit data
00911 #define SSI_CR0_DSS_12 0x0000000B ///< 12-bit data
00912 #define SSI_CR0_DSS_13 0x0000000C ///< 13-bit data
00913 #define SSI_CR0_DSS_14 0x0000000D ///< 14-bit data
00914 #define SSI_CR0_DSS_15 0x0000000E ///< 15-bit data
00915 #define SSI_CR0_DSS_16 0x0000000F ///< 16-bit data
00916 #define SSI_CR0_SCR_S 8
00917
00918
00922
00923 #define SSI_CR1_SOD 0x00000008 ///< SSI Slave Mode Output Disable
00924 #define SSI_CR1_MS 0x00000004 ///< SSI Master/Slave Select
00925 #define SSI_CR1_SSE 0x00000002 ///< SSI Synchronous Serial Port
00926
00927 #define SSI_CR1_LBM 0x00000001 ///< SSI Loopback Mode
00928
00929
00933
00934 #define SSI_DR_DATA_M 0x0000FFFF ///< SSI Receive/Transmit Data
00935 #define SSI_DR_DATA_S 0
00936
00937
00941
00942 #define SSI_SR_BSY 0x00000010 ///< SSI Busy Bit
00943 #define SSI_SR_RFF 0x00000008 ///< SSI Receive FIFO Full
00944 #define SSI_SR_RNE 0x00000004 ///< SSI Receive FIFO Not Empty
00945 #define SSI_SR_TNF 0x00000002 ///< SSI Transmit FIFO Not Full
00946 #define SSI_SR_TFE 0x00000001 ///< SSI Transmit FIFO Empty
00947
00948
00952
00953 #define SSI_CPSR_CPSDVSR_M 0x000000FF ///< SSI Clock Prescale Divisor
00954 #define SSI_CPSR_CPSDVSR_S 0
00955
00956
00960
00961 #define SSI_IM_TXIM 0x00000008 ///< SSI Transmit FIFO Interrupt Mask
00962 #define SSI_IM_RXIM 0x00000004 ///< SSI Receive FIFO Interrupt Mask
00963 #define SSI_IM_RTIM 0x00000002 ///< SSI Receive Time-Out Interrupt
00964
00965 #define SSI_IM_RORIM 0x00000001 ///< SSI Receive Overrun Interrupt
00966
00967
00968
00972
00973 #define SSI_RIS_TXRIS 0x00000008 ///< SSI Transmit FIFO Raw Interrupt
00974
00975 #define SSI_RIS_RXRIS 0x00000004 ///< SSI Receive FIFO Raw Interrupt
00976
00977 #define SSI_RIS_RTRIS 0x00000002 ///< SSI Receive Time-Out Raw
00978
00979 #define SSI_RIS_RORRIS 0x00000001 ///< SSI Receive Overrun Raw
00980
00981
00982
00986
00987 #define SSI_MIS_TXMIS 0x00000008 ///< SSI Transmit FIFO Masked
00988
00989 #define SSI_MIS_RXMIS 0x00000004 ///< SSI Receive FIFO Masked
00990
00991 #define SSI_MIS_RTMIS 0x00000002 ///< SSI Receive Time-Out Masked
00992
00993 #define SSI_MIS_RORMIS 0x00000001 ///< SSI Receive Overrun Masked
00994
00995
00996
01000
01001 #define SSI_ICR_RTIC 0x00000002 ///< SSI Receive Time-Out Interrupt
01002
01003 #define SSI_ICR_RORIC 0x00000001 ///< SSI Receive Overrun Interrupt
01004
01005
01006
01010
01011 #define UART_DR_OE 0x00000800 ///< UART Overrun Error
01012 #define UART_DR_BE 0x00000400 ///< UART Break Error
01013 #define UART_DR_PE 0x00000200 ///< UART Parity Error
01014 #define UART_DR_FE 0x00000100 ///< UART Framing Error
01015 #define UART_DR_DATA_M 0x000000FF ///< Data Transmitted or Received
01016 #define UART_DR_DATA_S 0
01017
01018
01022
01023 #define UART_RSR_OE 0x00000008 ///< UART Overrun Error
01024 #define UART_RSR_BE 0x00000004 ///< UART Break Error
01025 #define UART_RSR_PE 0x00000002 ///< UART Parity Error
01026 #define UART_RSR_FE 0x00000001 ///< UART Framing Error
01027
01028
01032
01033 #define UART_ECR_DATA_M 0x000000FF ///< Error Clear
01034 #define UART_ECR_DATA_S 0
01035
01036
01040
01041 #define UART_FR_TXFE 0x00000080 ///< UART Transmit FIFO Empty
01042 #define UART_FR_RXFF 0x00000040 ///< UART Receive FIFO Full
01043 #define UART_FR_TXFF 0x00000020 ///< UART Transmit FIFO Full
01044 #define UART_FR_RXFE 0x00000010 ///< UART Receive FIFO Empty
01045 #define UART_FR_BUSY 0x00000008 ///< UART Busy
01046
01047
01051
01052 #define UART_ILPR_ILPDVSR_M 0x000000FF ///< IrDA Low-Power Divisor
01053 #define UART_ILPR_ILPDVSR_S 0
01054
01055
01059
01060 #define UART_IBRD_DIVINT_M 0x0000FFFF ///< Integer Baud-Rate Divisor
01061 #define UART_IBRD_DIVINT_S 0
01062
01063
01067
01068 #define UART_FBRD_DIVFRAC_M 0x0000003F ///< Fractional Baud-Rate Divisor
01069 #define UART_FBRD_DIVFRAC_S 0
01070
01071
01075
01076 #define UART_LCRH_SPS 0x00000080 ///< UART Stick Parity Select
01077 #define UART_LCRH_WLEN_M 0x00000060 ///< UART Word Length
01078 #define UART_LCRH_WLEN_5 0x00000000 ///< 5 bits (default)
01079 #define UART_LCRH_WLEN_6 0x00000020 ///< 6 bits
01080 #define UART_LCRH_WLEN_7 0x00000040 ///< 7 bits
01081 #define UART_LCRH_WLEN_8 0x00000060 ///< 8 bits
01082 #define UART_LCRH_FEN 0x00000010 ///< UART Enable FIFOs
01083 #define UART_LCRH_STP2 0x00000008 ///< UART Two Stop Bits Select
01084 #define UART_LCRH_EPS 0x00000004 ///< UART Even Parity Select
01085 #define UART_LCRH_PEN 0x00000002 ///< UART Parity Enable
01086 #define UART_LCRH_BRK 0x00000001 ///< UART Send Break
01087
01088
01092
01093 #define UART_CTL_RXE 0x00000200 ///< UART Receive Enable
01094 #define UART_CTL_TXE 0x00000100 ///< UART Transmit Enable
01095 #define UART_CTL_LBE 0x00000080 ///< UART Loop Back Enable
01096 #define UART_CTL_SIRLP 0x00000004 ///< UART SIR Low-Power Mode
01097 #define UART_CTL_SIREN 0x00000002 ///< UART SIR Enable
01098 #define UART_CTL_UARTEN 0x00000001 ///< UART Enable
01099
01100
01104
01105 #define UART_IFLS_RX_M 0x00000038 ///< UART Receive Interrupt FIFO
01106
01107 #define UART_IFLS_RX1_8 0x00000000 ///< RX FIFO >= 1/8 full
01108 #define UART_IFLS_RX2_8 0x00000008 ///< RX FIFO >= 1/4 full
01109 #define UART_IFLS_RX4_8 0x00000010 ///< RX FIFO >= 1/2 full (default)
01110 #define UART_IFLS_RX6_8 0x00000018 ///< RX FIFO >= 3/4 full
01111 #define UART_IFLS_RX7_8 0x00000020 ///< RX FIFO >= 7/8 full
01112 #define UART_IFLS_TX_M 0x00000007 ///< UART Transmit Interrupt FIFO
01113
01114 #define UART_IFLS_TX1_8 0x00000000 ///< TX FIFO <= 1/8 full
01115 #define UART_IFLS_TX2_8 0x00000001 ///< TX FIFO <= 1/4 full
01116 #define UART_IFLS_TX4_8 0x00000002 ///< TX FIFO <= 1/2 full (default)
01117 #define UART_IFLS_TX6_8 0x00000003 ///< TX FIFO <= 3/4 full
01118 #define UART_IFLS_TX7_8 0x00000004 ///< TX FIFO <= 7/8 full
01119
01120
01124
01125 #define UART_IM_OEIM 0x00000400 ///< UART Overrun Error Interrupt
01126
01127 #define UART_IM_BEIM 0x00000200 ///< UART Break Error Interrupt Mask
01128 #define UART_IM_PEIM 0x00000100 ///< UART Parity Error Interrupt Mask
01129 #define UART_IM_FEIM 0x00000080 ///< UART Framing Error Interrupt
01130
01131 #define UART_IM_RTIM 0x00000040 ///< UART Receive Time-Out Interrupt
01132
01133 #define UART_IM_TXIM 0x00000020 ///< UART Transmit Interrupt Mask
01134 #define UART_IM_RXIM 0x00000010 ///< UART Receive Interrupt Mask
01135
01136
01140
01141 #define UART_RIS_OERIS 0x00000400 ///< UART Overrun Error Raw Interrupt
01142
01143 #define UART_RIS_BERIS 0x00000200 ///< UART Break Error Raw Interrupt
01144
01145 #define UART_RIS_PERIS 0x00000100 ///< UART Parity Error Raw Interrupt
01146
01147 #define UART_RIS_FERIS 0x00000080 ///< UART Framing Error Raw Interrupt
01148
01149 #define UART_RIS_RTRIS 0x00000040 ///< UART Receive Time-Out Raw
01150
01151 #define UART_RIS_TXRIS 0x00000020 ///< UART Transmit Raw Interrupt
01152
01153 #define UART_RIS_RXRIS 0x00000010 ///< UART Receive Raw Interrupt
01154
01155
01156
01160
01161 #define UART_MIS_OEMIS 0x00000400 ///< UART Overrun Error Masked
01162
01163 #define UART_MIS_BEMIS 0x00000200 ///< UART Break Error Masked
01164
01165 #define UART_MIS_PEMIS 0x00000100 ///< UART Parity Error Masked
01166
01167 #define UART_MIS_FEMIS 0x00000080 ///< UART Framing Error Masked
01168
01169 #define UART_MIS_RTMIS 0x00000040 ///< UART Receive Time-Out Masked
01170
01171 #define UART_MIS_TXMIS 0x00000020 ///< UART Transmit Masked Interrupt
01172
01173 #define UART_MIS_RXMIS 0x00000010 ///< UART Receive Masked Interrupt
01174
01175
01176
01180
01181 #define UART_ICR_OEIC 0x00000400 ///< Overrun Error Interrupt Clear
01182 #define UART_ICR_BEIC 0x00000200 ///< Break Error Interrupt Clear
01183 #define UART_ICR_PEIC 0x00000100 ///< Parity Error Interrupt Clear
01184 #define UART_ICR_FEIC 0x00000080 ///< Framing Error Interrupt Clear
01185 #define UART_ICR_RTIC 0x00000040 ///< Receive Time-Out Interrupt Clear
01186 #define UART_ICR_TXIC 0x00000020 ///< Transmit Interrupt Clear
01187 #define UART_ICR_RXIC 0x00000010 ///< Receive Interrupt Clear
01188
01189
01193
01194 #define I2C_MSA_SA_M 0x000000FE ///< I2C Slave Address
01195 #define I2C_MSA_RS 0x00000001 ///< Receive not send
01196 #define I2C_MSA_SA_S 1
01197
01198
01202
01203 #define I2C_SOAR_OAR_M 0x0000007F ///< I2C Slave Own Address
01204 #define I2C_SOAR_OAR_S 0
01205
01206
01210
01211 #define I2C_SCSR_FBR 0x00000004 ///< First Byte Received
01212 #define I2C_SCSR_TREQ 0x00000002 ///< Transmit Request
01213 #define I2C_SCSR_DA 0x00000001 ///< Device Active
01214 #define I2C_SCSR_RREQ 0x00000001 ///< Receive Request
01215
01216
01220
01221 #define I2C_MCS_BUSBSY 0x00000040 ///< Bus Busy
01222 #define I2C_MCS_IDLE 0x00000020 ///< I2C Idle
01223 #define I2C_MCS_ARBLST 0x00000010 ///< Arbitration Lost
01224 #define I2C_MCS_ACK 0x00000008 ///< Data Acknowledge Enable
01225 #define I2C_MCS_DATACK 0x00000008 ///< Acknowledge Data
01226 #define I2C_MCS_ADRACK 0x00000004 ///< Acknowledge Address
01227 #define I2C_MCS_STOP 0x00000004 ///< Generate STOP
01228 #define I2C_MCS_START 0x00000002 ///< Generate START
01229 #define I2C_MCS_ERROR 0x00000002 ///< Error
01230 #define I2C_MCS_RUN 0x00000001 ///< I2C Master Enable
01231 #define I2C_MCS_BUSY 0x00000001 ///< I2C Busy
01232
01233
01237
01238 #define I2C_SDR_DATA_M 0x000000FF ///< Data for Transfer
01239 #define I2C_SDR_DATA_S 0
01240
01241
01245
01246 #define I2C_MDR_DATA_M 0x000000FF ///< Data Transferred
01247 #define I2C_MDR_DATA_S 0
01248
01249
01253
01254 #define I2C_MTPR_TPR_M 0x000000FF ///< SCL Clock Period
01255 #define I2C_MTPR_TPR_S 0
01256
01257
01261
01262 #define I2C_SIMR_DATAIM 0x00000001 ///< Data Interrupt Mask
01263
01264
01268
01269 #define I2C_SRIS_DATARIS 0x00000001 ///< Data Raw Interrupt Status
01270
01271
01275
01276 #define I2C_MIMR_IM 0x00000001 ///< Interrupt Mask
01277
01278
01282
01283 #define I2C_MRIS_RIS 0x00000001 ///< Raw Interrupt Status
01284
01285
01289
01290 #define I2C_SMIS_DATAMIS 0x00000001 ///< Data Masked Interrupt Status
01291
01292
01296
01297 #define I2C_SICR_DATAIC 0x00000001 ///< Data Interrupt Clear
01298
01299
01303
01304 #define I2C_MMIS_MIS 0x00000001 ///< Masked Interrupt Status
01305
01306
01310
01311 #define I2C_MICR_IC 0x00000001 ///< Interrupt Clear
01312
01313
01317
01318 #define I2C_MCR_SFE 0x00000020 ///< I2C Slave Function Enable
01319 #define I2C_MCR_MFE 0x00000010 ///< I2C Master Function Enable
01320 #define I2C_MCR_LPBK 0x00000001 ///< I2C Loopback
01321
01322
01326
01327 #define PWM_CTL_GLOBALSYNC2 0x00000004 ///< Update PWM Generator 2
01328 #define PWM_CTL_GLOBALSYNC1 0x00000002 ///< Update PWM Generator 1
01329 #define PWM_CTL_GLOBALSYNC0 0x00000001 ///< Update PWM Generator 0
01330
01331
01335
01336 #define PWM_SYNC_SYNC2 0x00000004 ///< Reset Generator 2 Counter
01337 #define PWM_SYNC_SYNC1 0x00000002 ///< Reset Generator 1 Counter
01338 #define PWM_SYNC_SYNC0 0x00000001 ///< Reset Generator 0 Counter
01339
01340
01344
01345 #define PWM_ENABLE_PWM5EN 0x00000020 ///< PWM5 Output Enable
01346 #define PWM_ENABLE_PWM4EN 0x00000010 ///< PWM4 Output Enable
01347 #define PWM_ENABLE_PWM3EN 0x00000008 ///< PWM3 Output Enable
01348 #define PWM_ENABLE_PWM2EN 0x00000004 ///< PWM2 Output Enable
01349 #define PWM_ENABLE_PWM1EN 0x00000002 ///< PWM1 Output Enable
01350 #define PWM_ENABLE_PWM0EN 0x00000001 ///< PWM0 Output Enable
01351
01352
01356
01357 #define PWM_INVERT_PWM5INV 0x00000020 ///< Invert PWM5 Signal
01358 #define PWM_INVERT_PWM4INV 0x00000010 ///< Invert PWM4 Signal
01359 #define PWM_INVERT_PWM3INV 0x00000008 ///< Invert PWM3 Signal
01360 #define PWM_INVERT_PWM2INV 0x00000004 ///< Invert PWM2 Signal
01361 #define PWM_INVERT_PWM1INV 0x00000002 ///< Invert PWM1 Signal
01362 #define PWM_INVERT_PWM0INV 0x00000001 ///< Invert PWM0 Signal
01363
01364
01368
01369 #define PWM_FAULT_FAULT5 0x00000020 ///< PWM5 Fault
01370 #define PWM_FAULT_FAULT4 0x00000010 ///< PWM4 Fault
01371 #define PWM_FAULT_FAULT3 0x00000008 ///< PWM3 Fault
01372 #define PWM_FAULT_FAULT2 0x00000004 ///< PWM2 Fault
01373 #define PWM_FAULT_FAULT1 0x00000002 ///< PWM1 Fault
01374 #define PWM_FAULT_FAULT0 0x00000001 ///< PWM0 Fault
01375
01376
01380
01381 #define PWM_INTEN_INTFAULT 0x00010000 ///< Fault Interrupt Enable
01382 #define PWM_INTEN_INTPWM2 0x00000004 ///< PWM2 Interrupt Enable
01383 #define PWM_INTEN_INTPWM1 0x00000002 ///< PWM1 Interrupt Enable
01384 #define PWM_INTEN_INTPWM0 0x00000001 ///< PWM0 Interrupt Enable
01385
01386
01390
01391 #define PWM_RIS_INTFAULT 0x00010000 ///< Fault Interrupt Asserted
01392 #define PWM_RIS_INTPWM2 0x00000004 ///< PWM2 Interrupt Asserted
01393 #define PWM_RIS_INTPWM1 0x00000002 ///< PWM1 Interrupt Asserted
01394 #define PWM_RIS_INTPWM0 0x00000001 ///< PWM0 Interrupt Asserted
01395
01396
01400
01401 #define PWM_ISC_INTFAULT 0x00010000 ///< Fault Interrupt Asserted
01402 #define PWM_ISC_INTPWM2 0x00000004 ///< PWM2 Interrupt Status
01403 #define PWM_ISC_INTPWM1 0x00000002 ///< PWM1 Interrupt Status
01404 #define PWM_ISC_INTPWM0 0x00000001 ///< PWM0 Interrupt Status
01405
01406
01410
01411 #define PWM_STATUS_FAULT 0x00000001 ///< Fault Interrupt Status
01412
01413
01417
01418 #define PWM_X_CTL_CMPBUPD 0x00000020 ///< Comparator B Update Mode
01419 #define PWM_X_CTL_CMPAUPD 0x00000010 ///< Comparator A Update Mode
01420 #define PWM_X_CTL_LOADUPD 0x00000008 ///< Load Register Update Mode
01421 #define PWM_X_CTL_DEBUG 0x00000004 ///< Debug Mode
01422 #define PWM_X_CTL_MODE 0x00000002 ///< Counter Mode
01423 #define PWM_X_CTL_ENABLE 0x00000001 ///< PWM Block Enable
01424
01425
01429
01430 #define PWM_X_INTEN_TRCMPBD 0x00002000 ///< Trigger for Counter=PWMnCMPB
01431
01432 #define PWM_X_INTEN_TRCMPBU 0x00001000 ///< Trigger for Counter=PWMnCMPB Up
01433 #define PWM_X_INTEN_TRCMPAD 0x00000800 ///< Trigger for Counter=PWMnCMPA
01434
01435 #define PWM_X_INTEN_TRCMPAU 0x00000400 ///< Trigger for Counter=PWMnCMPA Up
01436 #define PWM_X_INTEN_TRCNTLOAD 0x00000200 ///< Trigger for Counter=PWMnLOAD
01437 #define PWM_X_INTEN_TRCNTZERO 0x00000100 ///< Trigger for Counter=0
01438 #define PWM_X_INTEN_INTCMPBD 0x00000020 ///< Interrupt for Counter=PWMnCMPB
01439
01440 #define PWM_X_INTEN_INTCMPBU 0x00000010 ///< Interrupt for Counter=PWMnCMPB
01441
01442 #define PWM_X_INTEN_INTCMPAD 0x00000008 ///< Interrupt for Counter=PWMnCMPA
01443
01444 #define PWM_X_INTEN_INTCMPAU 0x00000004 ///< Interrupt for Counter=PWMnCMPA
01445
01446 #define PWM_X_INTEN_INTCNTLOAD 0x00000002 ///< Interrupt for Counter=PWMnLOAD
01447 #define PWM_X_INTEN_INTCNTZERO 0x00000001 ///< Interrupt for Counter=0
01448
01449
01453
01454 #define PWM_X_RIS_INTCMPBD 0x00000020 ///< Comparator B Down Interrupt
01455
01456 #define PWM_X_RIS_INTCMPBU 0x00000010 ///< Comparator B Up Interrupt Status
01457 #define PWM_X_RIS_INTCMPAD 0x00000008 ///< Comparator A Down Interrupt
01458
01459 #define PWM_X_RIS_INTCMPAU 0x00000004 ///< Comparator A Up Interrupt Status
01460 #define PWM_X_RIS_INTCNTLOAD 0x00000002 ///< Counter=Load Interrupt Status
01461 #define PWM_X_RIS_INTCNTZERO 0x00000001 ///< Counter=0 Interrupt Status
01462
01463
01467
01468 #define PWM_X_ISC_INTCMPBD 0x00000020 ///< Comparator B Down Interrupt
01469 #define PWM_X_ISC_INTCMPBU 0x00000010 ///< Comparator B Up Interrupt
01470 #define PWM_X_ISC_INTCMPAD 0x00000008 ///< Comparator A Down Interrupt
01471 #define PWM_X_ISC_INTCMPAU 0x00000004 ///< Comparator A Up Interrupt
01472 #define PWM_X_ISC_INTCNTLOAD 0x00000002 ///< Counter=Load Interrupt
01473 #define PWM_X_ISC_INTCNTZERO 0x00000001 ///< Counter=0 Interrupt
01474
01475
01479
01480 #define PWM_X_LOAD_M 0x0000FFFF ///< Counter Load Value
01481 #define PWM_X_LOAD_S 0
01482
01483
01487
01488 #define PWM_X_COUNT_M 0x0000FFFF ///< Counter Value
01489 #define PWM_X_COUNT_S 0
01490
01491
01495
01496 #define PWM_X_CMPA_M 0x0000FFFF ///< Comparator A Value
01497 #define PWM_X_CMPA_S 0
01498
01499
01503
01504 #define PWM_X_CMPB_M 0x0000FFFF ///< Comparator B Value
01505 #define PWM_X_CMPB_S 0
01506
01507
01511
01512 #define PWM_X_GENA_ACTCMPBD_M 0x00000C00 ///< Action for Comparator B Down
01513 #define PWM_X_GENA_ACTCMPBD_NONE 0x00000000 ///< Do nothing
01514 #define PWM_X_GENA_ACTCMPBD_INV 0x00000400 ///< Invert pwmA
01515 #define PWM_X_GENA_ACTCMPBD_ZERO 0x00000800 ///< Drive pwmA Low
01516 #define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 ///< Drive pwmA High
01517 #define PWM_X_GENA_ACTCMPBU_M 0x00000300 ///< Action for Comparator B Up
01518 #define PWM_X_GENA_ACTCMPBU_NONE 0x00000000 ///< Do nothing
01519 #define PWM_X_GENA_ACTCMPBU_INV 0x00000100 ///< Invert pwmA
01520 #define PWM_X_GENA_ACTCMPBU_ZERO 0x00000200 ///< Drive pwmA Low
01521 #define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 ///< Drive pwmA High
01522 #define PWM_X_GENA_ACTCMPAD_M 0x000000C0 ///< Action for Comparator A Down
01523 #define PWM_X_GENA_ACTCMPAD_NONE 0x00000000 ///< Do nothing
01524 #define PWM_X_GENA_ACTCMPAD_INV 0x00000040 ///< Invert pwmA
01525 #define PWM_X_GENA_ACTCMPAD_ZERO 0x00000080 ///< Drive pwmA Low
01526 #define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 ///< Drive pwmA High
01527 #define PWM_X_GENA_ACTCMPAU_M 0x00000030 ///< Action for Comparator A Up
01528 #define PWM_X_GENA_ACTCMPAU_NONE 0x00000000 ///< Do nothing
01529 #define PWM_X_GENA_ACTCMPAU_INV 0x00000010 ///< Invert pwmA
01530 #define PWM_X_GENA_ACTCMPAU_ZERO 0x00000020 ///< Drive pwmA Low
01531 #define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 ///< Drive pwmA High
01532 #define PWM_X_GENA_ACTLOAD_M 0x0000000C ///< Action for Counter=LOAD
01533 #define PWM_X_GENA_ACTLOAD_NONE 0x00000000 ///< Do nothing
01534 #define PWM_X_GENA_ACTLOAD_INV 0x00000004 ///< Invert pwmA
01535 #define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 ///< Drive pwmA Low
01536 #define PWM_X_GENA_ACTLOAD_ONE 0x0000000C ///< Drive pwmA High
01537 #define PWM_X_GENA_ACTZERO_M 0x00000003 ///< Action for Counter=0
01538 #define PWM_X_GENA_ACTZERO_NONE 0x00000000 ///< Do nothing
01539 #define PWM_X_GENA_ACTZERO_INV 0x00000001 ///< Invert pwmA
01540 #define PWM_X_GENA_ACTZERO_ZERO 0x00000002 ///< Drive pwmA Low
01541 #define PWM_X_GENA_ACTZERO_ONE 0x00000003 ///< Drive pwmA High
01542
01543
01547
01548 #define PWM_X_GENB_ACTCMPBD_M 0x00000C00 ///< Action for Comparator B Down
01549 #define PWM_X_GENB_ACTCMPBD_NONE 0x00000000 ///< Do nothing
01550 #define PWM_X_GENB_ACTCMPBD_INV 0x00000400 ///< Invert pwmB
01551 #define PWM_X_GENB_ACTCMPBD_ZERO 0x00000800 ///< Drive pwmB Low
01552 #define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 ///< Drive pwmB High
01553 #define PWM_X_GENB_ACTCMPBU_M 0x00000300 ///< Action for Comparator B Up
01554 #define PWM_X_GENB_ACTCMPBU_NONE 0x00000000 ///< Do nothing
01555 #define PWM_X_GENB_ACTCMPBU_INV 0x00000100 ///< Invert pwmB
01556 #define PWM_X_GENB_ACTCMPBU_ZERO 0x00000200 ///< Drive pwmB Low
01557 #define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 ///< Drive pwmB High
01558 #define PWM_X_GENB_ACTCMPAD_M 0x000000C0 ///< Action for Comparator A Down
01559 #define PWM_X_GENB_ACTCMPAD_NONE 0x00000000 ///< Do nothing
01560 #define PWM_X_GENB_ACTCMPAD_INV 0x00000040 ///< Invert pwmB
01561 #define PWM_X_GENB_ACTCMPAD_ZERO 0x00000080 ///< Drive pwmB Low
01562 #define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 ///< Drive pwmB High
01563 #define PWM_X_GENB_ACTCMPAU_M 0x00000030 ///< Action for Comparator A Up
01564 #define PWM_X_GENB_ACTCMPAU_NONE 0x00000000 ///< Do nothing
01565 #define PWM_X_GENB_ACTCMPAU_INV 0x00000010 ///< Invert pwmB
01566 #define PWM_X_GENB_ACTCMPAU_ZERO 0x00000020 ///< Drive pwmB Low
01567 #define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 ///< Drive pwmB High
01568 #define PWM_X_GENB_ACTLOAD_M 0x0000000C ///< Action for Counter=LOAD
01569 #define PWM_X_GENB_ACTLOAD_NONE 0x00000000 ///< Do nothing
01570 #define PWM_X_GENB_ACTLOAD_INV 0x00000004 ///< Invert pwmB
01571 #define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 ///< Drive pwmB Low
01572 #define PWM_X_GENB_ACTLOAD_ONE 0x0000000C ///< Drive pwmB High
01573 #define PWM_X_GENB_ACTZERO_M 0x00000003 ///< Action for Counter=0
01574 #define PWM_X_GENB_ACTZERO_NONE 0x00000000 ///< Do nothing
01575 #define PWM_X_GENB_ACTZERO_INV 0x00000001 ///< Invert pwmB
01576 #define PWM_X_GENB_ACTZERO_ZERO 0x00000002 ///< Drive pwmB Low
01577 #define PWM_X_GENB_ACTZERO_ONE 0x00000003 ///< Drive pwmB High
01578
01579
01583
01584 #define PWM_X_DBCTL_ENABLE 0x00000001 ///< Dead-Band Generator Enable
01585
01586
01590
01591 #define PWM_X_DBRISE_DELAY_M 0x00000FFF ///< Dead-Band Rise Delay
01592 #define PWM_X_DBRISE_DELAY_S 0
01593
01594
01598
01599 #define PWM_X_DBFALL_DELAY_M 0x00000FFF ///< Dead-Band Fall Delay
01600 #define PWM_X_DBFALL_DELAY_S 0
01601
01602
01606
01607 #define QEI_CTL_STALLEN 0x00001000 ///< Stall QEI
01608 #define QEI_CTL_INVI 0x00000800 ///< Invert Index Pulse
01609 #define QEI_CTL_INVB 0x00000400 ///< Invert PhB
01610 #define QEI_CTL_INVA 0x00000200 ///< Invert PhA
01611 #define QEI_CTL_VELDIV_M 0x000001C0 ///< Predivide Velocity
01612 #define QEI_CTL_VELDIV_1 0x00000000 ///< QEI clock /1
01613 #define QEI_CTL_VELDIV_2 0x00000040 ///< QEI clock /2
01614 #define QEI_CTL_VELDIV_4 0x00000080 ///< QEI clock /4
01615 #define QEI_CTL_VELDIV_8 0x000000C0 ///< QEI clock /8
01616 #define QEI_CTL_VELDIV_16 0x00000100 ///< QEI clock /16
01617 #define QEI_CTL_VELDIV_32 0x00000140 ///< QEI clock /32
01618 #define QEI_CTL_VELDIV_64 0x00000180 ///< QEI clock /64
01619 #define QEI_CTL_VELDIV_128 0x000001C0 ///< QEI clock /128
01620 #define QEI_CTL_VELEN 0x00000020 ///< Capture Velocity
01621 #define QEI_CTL_RESMODE 0x00000010 ///< Reset Mode
01622 #define QEI_CTL_CAPMODE 0x00000008 ///< Capture Mode
01623 #define QEI_CTL_SIGMODE 0x00000004 ///< Signal Mode
01624 #define QEI_CTL_SWAP 0x00000002 ///< Swap Signals
01625 #define QEI_CTL_ENABLE 0x00000001 ///< Enable QEI
01626
01627
01631
01632 #define QEI_STAT_DIRECTION 0x00000002 ///< Direction of Rotation
01633 #define QEI_STAT_ERROR 0x00000001 ///< Error Detected
01634
01635
01639
01640 #define QEI_POS_M 0xFFFFFFFF ///< Current Position Integrator Value
01641 #define QEI_POS_S 0
01642
01643
01647
01648 #define QEI_MAXPOS_M 0xFFFFFFFF ///< Maximum Position Integrator Value
01649 #define QEI_MAXPOS_S 0
01650
01651
01655
01656 #define QEI_LOAD_M 0xFFFFFFFF ///< Velocity Timer Load Value
01657 #define QEI_LOAD_S 0
01658
01659
01663
01664 #define QEI_TIME_M 0xFFFFFFFF ///< Velocity Timer Current Value
01665 #define QEI_TIME_S 0
01666
01667
01671
01672 #define QEI_COUNT_M 0xFFFFFFFF ///< Velocity Pulse Count
01673 #define QEI_COUNT_S 0
01674
01675
01679
01680 #define QEI_SPEED_M 0xFFFFFFFF ///< Velocity
01681 #define QEI_SPEED_S 0
01682
01683
01687
01688 #define QEI_INTEN_ERROR 0x00000008 ///< Phase Error Interrupt Enable
01689 #define QEI_INTEN_DIR 0x00000004 ///< Direction Change Interrupt
01690
01691 #define QEI_INTEN_TIMER 0x00000002 ///< Timer Expires Interrupt Enable
01692 #define QEI_INTEN_INDEX 0x00000001 ///< Index Pulse Detected Interrupt
01693
01694
01695
01699
01700 #define QEI_RIS_ERROR 0x00000008 ///< Phase Error Detected
01701 #define QEI_RIS_DIR 0x00000004 ///< Direction Change Detected
01702 #define QEI_RIS_TIMER 0x00000002 ///< Velocity Timer Expired
01703 #define QEI_RIS_INDEX 0x00000001 ///< Index Pulse Asserted
01704
01705
01709
01710 #define QEI_ISC_ERROR 0x00000008 ///< Phase Error Interrupt
01711 #define QEI_ISC_DIR 0x00000004 ///< Direction Change Interrupt
01712 #define QEI_ISC_TIMER 0x00000002 ///< Velocity Timer Expired Interrupt
01713 #define QEI_ISC_INDEX 0x00000001 ///< Index Pulse Interrupt
01714
01715
01719
01720 #define TIMER_CFG_M 0x00000007 ///< GPTM Configuration
01721 #define TIMER_CFG_32_BIT_TIMER 0x00000000 ///< 32-bit timer configuration
01722 #define TIMER_CFG_32_BIT_RTC 0x00000001 ///< 32-bit real-time clock (RTC)
01723
01724 #define TIMER_CFG_16_BIT 0x00000004 ///< 16-bit timer configuration. The
01725
01726
01727
01728
01732
01733 #define TIMER_TAMR_TAAMS 0x00000008 ///< GPTM Timer A Alternate Mode
01734
01735 #define TIMER_TAMR_TACMR 0x00000004 ///< GPTM Timer A Capture Mode
01736 #define TIMER_TAMR_TAMR_M 0x00000003 ///< GPTM Timer A Mode
01737 #define TIMER_TAMR_TAMR_1_SHOT 0x00000001 ///< One-Shot Timer mode
01738 #define TIMER_TAMR_TAMR_PERIOD 0x00000002 ///< Periodic Timer mode
01739 #define TIMER_TAMR_TAMR_CAP 0x00000003 ///< Capture mode
01740
01741
01745
01746 #define TIMER_TBMR_TBAMS 0x00000008 ///< GPTM Timer B Alternate Mode
01747
01748 #define TIMER_TBMR_TBCMR 0x00000004 ///< GPTM Timer B Capture Mode
01749 #define TIMER_TBMR_TBMR_M 0x00000003 ///< GPTM Timer B Mode
01750 #define TIMER_TBMR_TBMR_1_SHOT 0x00000001 ///< One-Shot Timer mode
01751 #define TIMER_TBMR_TBMR_PERIOD 0x00000002 ///< Periodic Timer mode
01752 #define TIMER_TBMR_TBMR_CAP 0x00000003 ///< Capture mode
01753
01754
01758
01759 #define TIMER_CTL_TBPWML 0x00004000 ///< GPTM Timer B PWM Output Level
01760 #define TIMER_CTL_TBOTE 0x00002000 ///< GPTM Timer B Output Trigger
01761
01762 #define TIMER_CTL_TBEVENT_M 0x00000C00 ///< GPTM Timer B Event Mode
01763 #define TIMER_CTL_TBEVENT_POS 0x00000000 ///< Positive edge
01764 #define TIMER_CTL_TBEVENT_NEG 0x00000400 ///< Negative edge
01765 #define TIMER_CTL_TBEVENT_BOTH 0x00000C00 ///< Both edges
01766 #define TIMER_CTL_TBSTALL 0x00000200 ///< GPTM Timer B Stall Enable
01767 #define TIMER_CTL_TBEN 0x00000100 ///< GPTM Timer B Enable
01768 #define TIMER_CTL_TAPWML 0x00000040 ///< GPTM Timer A PWM Output Level
01769 #define TIMER_CTL_TAOTE 0x00000020 ///< GPTM Timer A Output Trigger
01770
01771 #define TIMER_CTL_RTCEN 0x00000010 ///< GPTM RTC Enable
01772 #define TIMER_CTL_TAEVENT_M 0x0000000C ///< GPTM Timer A Event Mode
01773 #define TIMER_CTL_TAEVENT_POS 0x00000000 ///< Positive edge
01774 #define TIMER_CTL_TAEVENT_NEG 0x00000004 ///< Negative edge
01775 #define TIMER_CTL_TAEVENT_BOTH 0x0000000C ///< Both edges
01776 #define TIMER_CTL_TASTALL 0x00000002 ///< GPTM Timer A Stall Enable
01777 #define TIMER_CTL_TAEN 0x00000001 ///< GPTM Timer A Enable
01778
01779
01783
01784 #define TIMER_IMR_CBEIM 0x00000400 ///< GPTM Capture B Event Interrupt
01785
01786 #define TIMER_IMR_CBMIM 0x00000200 ///< GPTM Capture B Match Interrupt
01787
01788 #define TIMER_IMR_TBTOIM 0x00000100 ///< GPTM Timer B Time-Out Interrupt
01789
01790 #define TIMER_IMR_RTCIM 0x00000008 ///< GPTM RTC Interrupt Mask
01791 #define TIMER_IMR_CAEIM 0x00000004 ///< GPTM Capture A Event Interrupt
01792
01793 #define TIMER_IMR_CAMIM 0x00000002 ///< GPTM Capture A Match Interrupt
01794
01795 #define TIMER_IMR_TATOIM 0x00000001 ///< GPTM Timer A Time-Out Interrupt
01796
01797
01798
01802
01803 #define TIMER_RIS_CBERIS 0x00000400 ///< GPTM Capture B Event Raw
01804
01805 #define TIMER_RIS_CBMRIS 0x00000200 ///< GPTM Capture B Match Raw
01806
01807 #define TIMER_RIS_TBTORIS 0x00000100 ///< GPTM Timer B Time-Out Raw
01808
01809 #define TIMER_RIS_RTCRIS 0x00000008 ///< GPTM RTC Raw Interrupt
01810 #define TIMER_RIS_CAERIS 0x00000004 ///< GPTM Capture A Event Raw
01811
01812 #define TIMER_RIS_CAMRIS 0x00000002 ///< GPTM Capture A Match Raw
01813
01814 #define TIMER_RIS_TATORIS 0x00000001 ///< GPTM Timer A Time-Out Raw
01815
01816
01817
01821
01822 #define TIMER_MIS_CBEMIS 0x00000400 ///< GPTM Capture B Event Masked
01823
01824 #define TIMER_MIS_CBMMIS 0x00000200 ///< GPTM Capture B Match Masked
01825
01826 #define TIMER_MIS_TBTOMIS 0x00000100 ///< GPTM Timer B Time-Out Masked
01827
01828 #define TIMER_MIS_RTCMIS 0x00000008 ///< GPTM RTC Masked Interrupt
01829 #define TIMER_MIS_CAEMIS 0x00000004 ///< GPTM Capture A Event Masked
01830
01831 #define TIMER_MIS_CAMMIS 0x00000002 ///< GPTM Capture A Match Masked
01832
01833 #define TIMER_MIS_TATOMIS 0x00000001 ///< GPTM Timer A Time-Out Masked
01834
01835
01836
01840
01841 #define TIMER_ICR_CBECINT 0x00000400 ///< GPTM Capture B Event Interrupt
01842
01843 #define TIMER_ICR_CBMCINT 0x00000200 ///< GPTM Capture B Match Interrupt
01844
01845 #define TIMER_ICR_TBTOCINT 0x00000100 ///< GPTM Timer B Time-Out Interrupt
01846
01847 #define TIMER_ICR_RTCCINT 0x00000008 ///< GPTM RTC Interrupt Clear
01848 #define TIMER_ICR_CAECINT 0x00000004 ///< GPTM Capture A Event Interrupt
01849
01850 #define TIMER_ICR_CAMCINT 0x00000002 ///< GPTM Capture A Match Interrupt
01851
01852 #define TIMER_ICR_TATOCINT 0x00000001 ///< GPTM Timer A Time-Out Raw
01853
01854
01855
01859
01860 #define TIMER_TAILR_TAILRH_M 0xFFFF0000 ///< GPTM Timer A Interval Load
01861
01862 #define TIMER_TAILR_TAILRL_M 0x0000FFFF ///< GPTM Timer A Interval Load
01863
01864 #define TIMER_TAILR_TAILRH_S 16
01865 #define TIMER_TAILR_TAILRL_S 0
01866
01867
01871
01872 #define TIMER_TBILR_TBILRL_M 0x0000FFFF ///< GPTM Timer B Interval Load
01873
01874 #define TIMER_TBILR_TBILRL_S 0
01875
01876
01881
01882 #define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 ///< GPTM Timer A Match Register High
01883 #define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF ///< GPTM Timer A Match Register Low
01884 #define TIMER_TAMATCHR_TAMRH_S 16
01885 #define TIMER_TAMATCHR_TAMRL_S 0
01886
01887
01892
01893 #define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF ///< GPTM Timer B Match Register Low
01894 #define TIMER_TBMATCHR_TBMRL_S 0
01895
01896
01900
01901 #define TIMER_TAPR_TAPSR_M 0x000000FF ///< GPTM Timer A Prescale
01902 #define TIMER_TAPR_TAPSR_S 0
01903
01904
01908
01909 #define TIMER_TBPR_TBPSR_M 0x000000FF ///< GPTM Timer B Prescale
01910 #define TIMER_TBPR_TBPSR_S 0
01911
01912
01916
01917 #define TIMER_TAPMR_TAPSMR_M 0x000000FF ///< GPTM TimerA Prescale Match
01918 #define TIMER_TAPMR_TAPSMR_S 0
01919
01920
01924
01925 #define TIMER_TBPMR_TBPSMR_M 0x000000FF ///< GPTM TimerB Prescale Match
01926 #define TIMER_TBPMR_TBPSMR_S 0
01927
01928
01932
01933 #define TIMER_TAR_TARH_M 0xFFFF0000 ///< GPTM Timer A Register High
01934 #define TIMER_TAR_TARL_M 0x0000FFFF ///< GPTM Timer A Register Low
01935 #define TIMER_TAR_TARH_S 16
01936 #define TIMER_TAR_TARL_S 0
01937
01938
01942
01943 #define TIMER_TBR_TBRL_M 0x0000FFFF ///< GPTM Timer B
01944 #define TIMER_TBR_TBRL_S 0
01945
01946
01950
01951 #define ADC_ACTSS_ASEN3 0x00000008 ///< ADC SS3 Enable
01952 #define ADC_ACTSS_ASEN2 0x00000004 ///< ADC SS2 Enable
01953 #define ADC_ACTSS_ASEN1 0x00000002 ///< ADC SS1 Enable
01954 #define ADC_ACTSS_ASEN0 0x00000001 ///< ADC SS0 Enable
01955
01956
01960
01961 #define ADC_RIS_INR3 0x00000008 ///< SS3 Raw Interrupt Status
01962 #define ADC_RIS_INR2 0x00000004 ///< SS2 Raw Interrupt Status
01963 #define ADC_RIS_INR1 0x00000002 ///< SS1 Raw Interrupt Status
01964 #define ADC_RIS_INR0 0x00000001 ///< SS0 Raw Interrupt Status
01965
01966
01970
01971 #define ADC_IM_MASK3 0x00000008 ///< SS3 Interrupt Mask
01972 #define ADC_IM_MASK2 0x00000004 ///< SS2 Interrupt Mask
01973 #define ADC_IM_MASK1 0x00000002 ///< SS1 Interrupt Mask
01974 #define ADC_IM_MASK0 0x00000001 ///< SS0 Interrupt Mask
01975
01976
01980
01981 #define ADC_ISC_IN3 0x00000008 ///< SS3 Interrupt Status and Clear
01982 #define ADC_ISC_IN2 0x00000004 ///< SS2 Interrupt Status and Clear
01983 #define ADC_ISC_IN1 0x00000002 ///< SS1 Interrupt Status and Clear
01984 #define ADC_ISC_IN0 0x00000001 ///< SS0 Interrupt Status and Clear
01985
01986
01990
01991 #define ADC_OSTAT_OV3 0x00000008 ///< SS3 FIFO Overflow
01992 #define ADC_OSTAT_OV2 0x00000004 ///< SS2 FIFO Overflow
01993 #define ADC_OSTAT_OV1 0x00000002 ///< SS1 FIFO Overflow
01994 #define ADC_OSTAT_OV0 0x00000001 ///< SS0 FIFO Overflow
01995
01996
02000
02001 #define ADC_EMUX_EM3_M 0x0000F000 ///< SS3 Trigger Select
02002 #define ADC_EMUX_EM3_PROCESSOR 0x00000000 ///< Processor (default)
02003 #define ADC_EMUX_EM3_COMP0 0x00001000 ///< Analog Comparator 0
02004 #define ADC_EMUX_EM3_COMP1 0x00002000 ///< Analog Comparator 1
02005 #define ADC_EMUX_EM3_COMP2 0x00003000 ///< Analog Comparator 2
02006 #define ADC_EMUX_EM3_EXTERNAL 0x00004000 ///< External (GPIO PB4)
02007 #define ADC_EMUX_EM3_TIMER 0x00005000 ///< Timer
02008 #define ADC_EMUX_EM3_PWM0 0x00006000 ///< PWM0
02009 #define ADC_EMUX_EM3_PWM1 0x00007000 ///< PWM1
02010 #define ADC_EMUX_EM3_PWM2 0x00008000 ///< PWM2
02011 #define ADC_EMUX_EM3_ALWAYS 0x0000F000 ///< Always (continuously sample)
02012 #define ADC_EMUX_EM2_M 0x00000F00 ///< SS2 Trigger Select
02013 #define ADC_EMUX_EM2_PROCESSOR 0x00000000 ///< Processor (default)
02014 #define ADC_EMUX_EM2_COMP0 0x00000100 ///< Analog Comparator 0
02015 #define ADC_EMUX_EM2_COMP1 0x00000200 ///< Analog Comparator 1
02016 #define ADC_EMUX_EM2_COMP2 0x00000300 ///< Analog Comparator 2
02017 #define ADC_EMUX_EM2_EXTERNAL 0x00000400 ///< External (GPIO PB4)
02018 #define ADC_EMUX_EM2_TIMER 0x00000500 ///< Timer
02019 #define ADC_EMUX_EM2_PWM0 0x00000600 ///< PWM0
02020 #define ADC_EMUX_EM2_PWM1 0x00000700 ///< PWM1
02021 #define ADC_EMUX_EM2_PWM2 0x00000800 ///< PWM2
02022 #define ADC_EMUX_EM2_ALWAYS 0x00000F00 ///< Always (continuously sample)
02023 #define ADC_EMUX_EM1_M 0x000000F0 ///< SS1 Trigger Select
02024 #define ADC_EMUX_EM1_PROCESSOR 0x00000000 ///< Processor (default)
02025 #define ADC_EMUX_EM1_COMP0 0x00000010 ///< Analog Comparator 0
02026 #define ADC_EMUX_EM1_COMP1 0x00000020 ///< Analog Comparator 1
02027 #define ADC_EMUX_EM1_COMP2 0x00000030 ///< Analog Comparator 2
02028 #define ADC_EMUX_EM1_EXTERNAL 0x00000040 ///< External (GPIO PB4)
02029 #define ADC_EMUX_EM1_TIMER 0x00000050 ///< Timer
02030 #define ADC_EMUX_EM1_PWM0 0x00000060 ///< PWM0
02031 #define ADC_EMUX_EM1_PWM1 0x00000070 ///< PWM1
02032 #define ADC_EMUX_EM1_PWM2 0x00000080 ///< PWM2
02033 #define ADC_EMUX_EM1_ALWAYS 0x000000F0 ///< Always (continuously sample)
02034 #define ADC_EMUX_EM0_M 0x0000000F ///< SS0 Trigger Select
02035 #define ADC_EMUX_EM0_PROCESSOR 0x00000000 ///< Processor (default)
02036 #define ADC_EMUX_EM0_COMP0 0x00000001 ///< Analog Comparator 0
02037 #define ADC_EMUX_EM0_COMP1 0x00000002 ///< Analog Comparator 1
02038 #define ADC_EMUX_EM0_COMP2 0x00000003 ///< Analog Comparator 2
02039 #define ADC_EMUX_EM0_EXTERNAL 0x00000004 ///< External (GPIO PB4)
02040 #define ADC_EMUX_EM0_TIMER 0x00000005 ///< Timer
02041 #define ADC_EMUX_EM0_PWM0 0x00000006 ///< PWM0
02042 #define ADC_EMUX_EM0_PWM1 0x00000007 ///< PWM1
02043 #define ADC_EMUX_EM0_PWM2 0x00000008 ///< PWM2
02044 #define ADC_EMUX_EM0_ALWAYS 0x0000000F ///< Always (continuously sample)
02045
02046
02050
02051 #define ADC_USTAT_UV3 0x00000008 ///< SS3 FIFO Underflow
02052 #define ADC_USTAT_UV2 0x00000004 ///< SS2 FIFO Underflow
02053 #define ADC_USTAT_UV1 0x00000002 ///< SS1 FIFO Underflow
02054 #define ADC_USTAT_UV0 0x00000001 ///< SS0 FIFO Underflow
02055
02056
02060
02061 #define ADC_SSPRI_SS3_M 0x00003000 ///< SS3 Priority
02062 #define ADC_SSPRI_SS3_1ST 0x00000000 ///< First priority
02063 #define ADC_SSPRI_SS3_2ND 0x00001000 ///< Second priority
02064 #define ADC_SSPRI_SS3_3RD 0x00002000 ///< Third priority
02065 #define ADC_SSPRI_SS3_4TH 0x00003000 ///< Fourth priority
02066 #define ADC_SSPRI_SS2_M 0x00000300 ///< SS2 Priority
02067 #define ADC_SSPRI_SS2_1ST 0x00000000 ///< First priority
02068 #define ADC_SSPRI_SS2_2ND 0x00000100 ///< Second priority
02069 #define ADC_SSPRI_SS2_3RD 0x00000200 ///< Third priority
02070 #define ADC_SSPRI_SS2_4TH 0x00000300 ///< Fourth priority
02071 #define ADC_SSPRI_SS1_M 0x00000030 ///< SS1 Priority
02072 #define ADC_SSPRI_SS1_1ST 0x00000000 ///< First priority
02073 #define ADC_SSPRI_SS1_2ND 0x00000010 ///< Second priority
02074 #define ADC_SSPRI_SS1_3RD 0x00000020 ///< Third priority
02075 #define ADC_SSPRI_SS1_4TH 0x00000030 ///< Fourth priority
02076 #define ADC_SSPRI_SS0_M 0x00000003 ///< SS0 Priority
02077 #define ADC_SSPRI_SS0_1ST 0x00000000 ///< First priority
02078 #define ADC_SSPRI_SS0_2ND 0x00000001 ///< Second priority
02079 #define ADC_SSPRI_SS0_3RD 0x00000002 ///< Third priority
02080 #define ADC_SSPRI_SS0_4TH 0x00000003 ///< Fourth priority
02081
02082
02086
02087 #define ADC_PSSI_SS3 0x00000008 ///< SS3 Initiate
02088 #define ADC_PSSI_SS2 0x00000004 ///< SS2 Initiate
02089 #define ADC_PSSI_SS1 0x00000002 ///< SS1 Initiate
02090 #define ADC_PSSI_SS0 0x00000001 ///< SS0 Initiate
02091
02092
02096
02097 #define ADC_SAC_AVG_M 0x00000007 ///< Hardware Averaging Control
02098 #define ADC_SAC_AVG_OFF 0x00000000 ///< No hardware oversampling
02099 #define ADC_SAC_AVG_2X 0x00000001 ///< 2x hardware oversampling
02100 #define ADC_SAC_AVG_4X 0x00000002 ///< 4x hardware oversampling
02101 #define ADC_SAC_AVG_8X 0x00000003 ///< 8x hardware oversampling
02102 #define ADC_SAC_AVG_16X 0x00000004 ///< 16x hardware oversampling
02103 #define ADC_SAC_AVG_32X 0x00000005 ///< 32x hardware oversampling
02104 #define ADC_SAC_AVG_64X 0x00000006 ///< 64x hardware oversampling
02105
02106
02110
02111 #define ADC_SSMUX0_MUX7_M 0x70000000 ///< 8th Sample Input Select
02112 #define ADC_SSMUX0_MUX6_M 0x07000000 ///< 7th Sample Input Select
02113 #define ADC_SSMUX0_MUX5_M 0x00700000 ///< 6th Sample Input Select
02114 #define ADC_SSMUX0_MUX4_M 0x00070000 ///< 5th Sample Input Select
02115 #define ADC_SSMUX0_MUX3_M 0x00007000 ///< 4th Sample Input Select
02116 #define ADC_SSMUX0_MUX2_M 0x00000700 ///< 3rd Sample Input Select
02117 #define ADC_SSMUX0_MUX1_M 0x00000070 ///< 2nd Sample Input Select
02118 #define ADC_SSMUX0_MUX0_M 0x00000007 ///< 1st Sample Input Select
02119 #define ADC_SSMUX0_MUX7_S 28
02120 #define ADC_SSMUX0_MUX6_S 24
02121 #define ADC_SSMUX0_MUX5_S 20
02122 #define ADC_SSMUX0_MUX4_S 16
02123 #define ADC_SSMUX0_MUX3_S 12
02124 #define ADC_SSMUX0_MUX2_S 8
02125 #define ADC_SSMUX0_MUX1_S 4
02126 #define ADC_SSMUX0_MUX0_S 0
02127
02128
02132
02133 #define ADC_SSCTL0_TS7 0x80000000 ///< 8th Sample Temp Sensor Select
02134 #define ADC_SSCTL0_IE7 0x40000000 ///< 8th Sample Interrupt Enable
02135 #define ADC_SSCTL0_END7 0x20000000 ///< 8th Sample is End of Sequence
02136 #define ADC_SSCTL0_D7 0x10000000 ///< 8th Sample Diff Input Select
02137 #define ADC_SSCTL0_TS6 0x08000000 ///< 7th Sample Temp Sensor Select
02138 #define ADC_SSCTL0_IE6 0x04000000 ///< 7th Sample Interrupt Enable
02139 #define ADC_SSCTL0_END6 0x02000000 ///< 7th Sample is End of Sequence
02140 #define ADC_SSCTL0_D6 0x01000000 ///< 7th Sample Diff Input Select
02141 #define ADC_SSCTL0_TS5 0x00800000 ///< 6th Sample Temp Sensor Select
02142 #define ADC_SSCTL0_IE5 0x00400000 ///< 6th Sample Interrupt Enable
02143 #define ADC_SSCTL0_END5 0x00200000 ///< 6th Sample is End of Sequence
02144 #define ADC_SSCTL0_D5 0x00100000 ///< 6th Sample Diff Input Select
02145 #define ADC_SSCTL0_TS4 0x00080000 ///< 5th Sample Temp Sensor Select
02146 #define ADC_SSCTL0_IE4 0x00040000 ///< 5th Sample Interrupt Enable
02147 #define ADC_SSCTL0_END4 0x00020000 ///< 5th Sample is End of Sequence
02148 #define ADC_SSCTL0_D4 0x00010000 ///< 5th Sample Diff Input Select
02149 #define ADC_SSCTL0_TS3 0x00008000 ///< 4th Sample Temp Sensor Select
02150 #define ADC_SSCTL0_IE3 0x00004000 ///< 4th Sample Interrupt Enable
02151 #define ADC_SSCTL0_END3 0x00002000 ///< 4th Sample is End of Sequence
02152 #define ADC_SSCTL0_D3 0x00001000 ///< 4th Sample Diff Input Select
02153 #define ADC_SSCTL0_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select
02154 #define ADC_SSCTL0_IE2 0x00000400 ///< 3rd Sample Interrupt Enable
02155 #define ADC_SSCTL0_END2 0x00000200 ///< 3rd Sample is End of Sequence
02156 #define ADC_SSCTL0_D2 0x00000100 ///< 3rd Sample Diff Input Select
02157 #define ADC_SSCTL0_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select
02158 #define ADC_SSCTL0_IE1 0x00000040 ///< 2nd Sample Interrupt Enable
02159 #define ADC_SSCTL0_END1 0x00000020 ///< 2nd Sample is End of Sequence
02160 #define ADC_SSCTL0_D1 0x00000010 ///< 2nd Sample Diff Input Select
02161 #define ADC_SSCTL0_TS0 0x00000008 ///< 1st Sample Temp Sensor Select
02162 #define ADC_SSCTL0_IE0 0x00000004 ///< 1st Sample Interrupt Enable
02163 #define ADC_SSCTL0_END0 0x00000002 ///< 1st Sample is End of Sequence
02164 #define ADC_SSCTL0_D0 0x00000001 ///< 1st Sample Diff Input Select
02165
02166
02170
02171 #define ADC_SSFIFO0_DATA_M 0x000003FF ///< Conversion Result Data
02172 #define ADC_SSFIFO0_DATA_S 0
02173
02174
02178
02179 #define ADC_SSFSTAT0_FULL 0x00001000 ///< FIFO Full
02180 #define ADC_SSFSTAT0_EMPTY 0x00000100 ///< FIFO Empty
02181 #define ADC_SSFSTAT0_HPTR_M 0x000000F0 ///< FIFO Head Pointer
02182 #define ADC_SSFSTAT0_TPTR_M 0x0000000F ///< FIFO Tail Pointer
02183 #define ADC_SSFSTAT0_HPTR_S 4
02184 #define ADC_SSFSTAT0_TPTR_S 0
02185
02186
02190
02191 #define ADC_SSMUX1_MUX3_M 0x00007000 ///< 4th Sample Input Select
02192 #define ADC_SSMUX1_MUX2_M 0x00000700 ///< 3rd Sample Input Select
02193 #define ADC_SSMUX1_MUX1_M 0x00000070 ///< 2nd Sample Input Select
02194 #define ADC_SSMUX1_MUX0_M 0x00000007 ///< 1st Sample Input Select
02195 #define ADC_SSMUX1_MUX3_S 12
02196 #define ADC_SSMUX1_MUX2_S 8
02197 #define ADC_SSMUX1_MUX1_S 4
02198 #define ADC_SSMUX1_MUX0_S 0
02199
02200
02204
02205 #define ADC_SSCTL1_TS3 0x00008000 ///< 4th Sample Temp Sensor Select
02206 #define ADC_SSCTL1_IE3 0x00004000 ///< 4th Sample Interrupt Enable
02207 #define ADC_SSCTL1_END3 0x00002000 ///< 4th Sample is End of Sequence
02208 #define ADC_SSCTL1_D3 0x00001000 ///< 4th Sample Diff Input Select
02209 #define ADC_SSCTL1_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select
02210 #define ADC_SSCTL1_IE2 0x00000400 ///< 3rd Sample Interrupt Enable
02211 #define ADC_SSCTL1_END2 0x00000200 ///< 3rd Sample is End of Sequence
02212 #define ADC_SSCTL1_D2 0x00000100 ///< 3rd Sample Diff Input Select
02213 #define ADC_SSCTL1_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select
02214 #define ADC_SSCTL1_IE1 0x00000040 ///< 2nd Sample Interrupt Enable
02215 #define ADC_SSCTL1_END1 0x00000020 ///< 2nd Sample is End of Sequence
02216 #define ADC_SSCTL1_D1 0x00000010 ///< 2nd Sample Diff Input Select
02217 #define ADC_SSCTL1_TS0 0x00000008 ///< 1st Sample Temp Sensor Select
02218 #define ADC_SSCTL1_IE0 0x00000004 ///< 1st Sample Interrupt Enable
02219 #define ADC_SSCTL1_END0 0x00000002 ///< 1st Sample is End of Sequence
02220 #define ADC_SSCTL1_D0 0x00000001 ///< 1st Sample Diff Input Select
02221
02222
02226
02227 #define ADC_SSFIFO1_DATA_M 0x000003FF ///< Conversion Result Data
02228 #define ADC_SSFIFO1_DATA_S 0
02229
02230
02234
02235 #define ADC_SSFSTAT1_FULL 0x00001000 ///< FIFO Full
02236 #define ADC_SSFSTAT1_EMPTY 0x00000100 ///< FIFO Empty
02237 #define ADC_SSFSTAT1_HPTR_M 0x000000F0 ///< FIFO Head Pointer
02238 #define ADC_SSFSTAT1_TPTR_M 0x0000000F ///< FIFO Tail Pointer
02239 #define ADC_SSFSTAT1_HPTR_S 4
02240 #define ADC_SSFSTAT1_TPTR_S 0
02241
02242
02246
02247 #define ADC_SSMUX2_MUX3_M 0x00007000 ///< 4th Sample Input Select
02248 #define ADC_SSMUX2_MUX2_M 0x00000700 ///< 3rd Sample Input Select
02249 #define ADC_SSMUX2_MUX1_M 0x00000070 ///< 2nd Sample Input Select
02250 #define ADC_SSMUX2_MUX0_M 0x00000007 ///< 1st Sample Input Select
02251 #define ADC_SSMUX2_MUX3_S 12
02252 #define ADC_SSMUX2_MUX2_S 8
02253 #define ADC_SSMUX2_MUX1_S 4
02254 #define ADC_SSMUX2_MUX0_S 0
02255
02256
02260
02261 #define ADC_SSCTL2_TS3 0x00008000 ///< 4th Sample Temp Sensor Select
02262 #define ADC_SSCTL2_IE3 0x00004000 ///< 4th Sample Interrupt Enable
02263 #define ADC_SSCTL2_END3 0x00002000 ///< 4th Sample is End of Sequence
02264 #define ADC_SSCTL2_D3 0x00001000 ///< 4th Sample Diff Input Select
02265 #define ADC_SSCTL2_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select
02266 #define ADC_SSCTL2_IE2 0x00000400 ///< 3rd Sample Interrupt Enable
02267 #define ADC_SSCTL2_END2 0x00000200 ///< 3rd Sample is End of Sequence
02268 #define ADC_SSCTL2_D2 0x00000100 ///< 3rd Sample Diff Input Select
02269 #define ADC_SSCTL2_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select
02270 #define ADC_SSCTL2_IE1 0x00000040 ///< 2nd Sample Interrupt Enable
02271 #define ADC_SSCTL2_END1 0x00000020 ///< 2nd Sample is End of Sequence
02272 #define ADC_SSCTL2_D1 0x00000010 ///< 2nd Sample Diff Input Select
02273 #define ADC_SSCTL2_TS0 0x00000008 ///< 1st Sample Temp Sensor Select
02274 #define ADC_SSCTL2_IE0 0x00000004 ///< 1st Sample Interrupt Enable
02275 #define ADC_SSCTL2_END0 0x00000002 ///< 1st Sample is End of Sequence
02276 #define ADC_SSCTL2_D0 0x00000001 ///< 1st Sample Diff Input Select
02277
02278
02282
02283 #define ADC_SSFIFO2_DATA_M 0x000003FF ///< Conversion Result Data
02284 #define ADC_SSFIFO2_DATA_S 0
02285
02286
02290
02291 #define ADC_SSFSTAT2_FULL 0x00001000 ///< FIFO Full
02292 #define ADC_SSFSTAT2_EMPTY 0x00000100 ///< FIFO Empty
02293 #define ADC_SSFSTAT2_HPTR_M 0x000000F0 ///< FIFO Head Pointer
02294 #define ADC_SSFSTAT2_TPTR_M 0x0000000F ///< FIFO Tail Pointer
02295 #define ADC_SSFSTAT2_HPTR_S 4
02296 #define ADC_SSFSTAT2_TPTR_S 0
02297
02298
02302
02303 #define ADC_SSMUX3_MUX0_M 0x00000007 ///< 1st Sample Input Select
02304 #define ADC_SSMUX3_MUX0_S 0
02305
02306
02310
02311 #define ADC_SSCTL3_TS0 0x00000008 ///< 1st Sample Temp Sensor Select
02312 #define ADC_SSCTL3_IE0 0x00000004 ///< 1st Sample Interrupt Enable
02313 #define ADC_SSCTL3_END0 0x00000002 ///< 1st Sample is End of Sequence
02314 #define ADC_SSCTL3_D0 0x00000001 ///< 1st Sample Diff Input Select
02315
02316
02320
02321 #define ADC_SSFIFO3_DATA_M 0x000003FF ///< Conversion Result Data
02322 #define ADC_SSFIFO3_DATA_S 0
02323
02324
02328
02329 #define ADC_SSFSTAT3_FULL 0x00001000 ///< FIFO Full
02330 #define ADC_SSFSTAT3_EMPTY 0x00000100 ///< FIFO Empty
02331 #define ADC_SSFSTAT3_HPTR_M 0x000000F0 ///< FIFO Head Pointer
02332 #define ADC_SSFSTAT3_TPTR_M 0x0000000F ///< FIFO Tail Pointer
02333 #define ADC_SSFSTAT3_HPTR_S 4
02334 #define ADC_SSFSTAT3_TPTR_S 0
02335
02336
02340
02341 #define ADC_TMLB_LB 0x00000001 ///< Loopback Mode Enable
02342
02343
02348
02349 #define ADC_SSFIFO_TMLB_CNT_M 0x000003C0 ///< Continuous Sample Counter
02350 #define ADC_SSFIFO_TMLB_CONT 0x00000020 ///< Continuation Sample Indicator
02351 #define ADC_SSFIFO_TMLB_DIFF 0x00000010 ///< Differential Sample Indicator
02352 #define ADC_SSFIFO_TMLB_TS 0x00000008 ///< Temp Sensor Sample Indicator
02353 #define ADC_SSFIFO_TMLB_MUX_M 0x00000007 ///< Analog Input Indicator
02354 #define ADC_SSFIFO_TMLB_CNT_S 6 ///< Sample counter shift
02355 #define ADC_SSFIFO_TMLB_MUX_S 0 ///< Input channel number shift
02356
02357
02361
02362 #define COMP_ACMIS_IN2 0x00000004 ///< Comparator 2 Masked Interrupt
02363
02364 #define COMP_ACMIS_IN1 0x00000002 ///< Comparator 1 Masked Interrupt
02365
02366 #define COMP_ACMIS_IN0 0x00000001 ///< Comparator 0 Masked Interrupt
02367
02368
02369
02373
02374 #define COMP_ACRIS_IN2 0x00000004 ///< Comparator 2 Interrupt Status
02375 #define COMP_ACRIS_IN1 0x00000002 ///< Comparator 1 Interrupt Status
02376 #define COMP_ACRIS_IN0 0x00000001 ///< Comparator 0 Interrupt Status
02377
02378
02382
02383 #define COMP_ACINTEN_IN2 0x00000004 ///< Comparator 2 Interrupt Enable
02384 #define COMP_ACINTEN_IN1 0x00000002 ///< Comparator 1 Interrupt Enable
02385 #define COMP_ACINTEN_IN0 0x00000001 ///< Comparator 0 Interrupt Enable
02386
02387
02392
02393 #define COMP_ACREFCTL_EN 0x00000200 ///< Resistor Ladder Enable
02394 #define COMP_ACREFCTL_RNG 0x00000100 ///< Resistor Ladder Range
02395 #define COMP_ACREFCTL_VREF_M 0x0000000F ///< Resistor Ladder Voltage Ref
02396 #define COMP_ACREFCTL_VREF_S 0
02397
02398
02402
02403 #define COMP_ACSTAT0_OVAL 0x00000002 ///< Comparator Output Value
02404
02405
02409
02410 #define COMP_ACCTL0_TOEN 0x00000800 ///< Trigger Output Enable
02411 #define COMP_ACCTL0_ASRCP_M 0x00000600 ///< Analog Source Positive
02412 #define COMP_ACCTL0_ASRCP_PIN 0x00000000 ///< Pin value of Cn+
02413 #define COMP_ACCTL0_ASRCP_PIN0 0x00000200 ///< Pin value of C0+
02414 #define COMP_ACCTL0_ASRCP_REF 0x00000400 ///< Internal voltage reference
02415
02416 #define COMP_ACCTL0_TSLVAL 0x00000080 ///< Trigger Sense Level Value
02417 #define COMP_ACCTL0_TSEN_M 0x00000060 ///< Trigger Sense
02418 #define COMP_ACCTL0_TSEN_LEVEL 0x00000000 ///< Level sense, see TSLVAL
02419 #define COMP_ACCTL0_TSEN_FALL 0x00000020 ///< Falling edge
02420 #define COMP_ACCTL0_TSEN_RISE 0x00000040 ///< Rising edge
02421 #define COMP_ACCTL0_TSEN_BOTH 0x00000060 ///< Either edge
02422 #define COMP_ACCTL0_ISLVAL 0x00000010 ///< Interrupt Sense Level Value
02423 #define COMP_ACCTL0_ISEN_M 0x0000000C ///< Interrupt Sense
02424 #define COMP_ACCTL0_ISEN_LEVEL 0x00000000 ///< Level sense, see ISLVAL
02425 #define COMP_ACCTL0_ISEN_FALL 0x00000004 ///< Falling edge
02426 #define COMP_ACCTL0_ISEN_RISE 0x00000008 ///< Rising edge
02427 #define COMP_ACCTL0_ISEN_BOTH 0x0000000C ///< Either edge
02428 #define COMP_ACCTL0_CINV 0x00000002 ///< Comparator Output Invert
02429
02430
02434
02435 #define COMP_ACSTAT1_OVAL 0x00000002 ///< Comparator Output Value
02436
02437
02441
02442 #define COMP_ACCTL1_TOEN 0x00000800 ///< Trigger Output Enable
02443 #define COMP_ACCTL1_ASRCP_M 0x00000600 ///< Analog Source Positive
02444 #define COMP_ACCTL1_ASRCP_PIN 0x00000000 ///< Pin value of Cn+
02445 #define COMP_ACCTL1_ASRCP_PIN0 0x00000200 ///< Pin value of C0+
02446 #define COMP_ACCTL1_ASRCP_REF 0x00000400 ///< Internal voltage reference
02447
02448 #define COMP_ACCTL1_TSLVAL 0x00000080 ///< Trigger Sense Level Value
02449 #define COMP_ACCTL1_TSEN_M 0x00000060 ///< Trigger Sense
02450 #define COMP_ACCTL1_TSEN_LEVEL 0x00000000 ///< Level sense, see TSLVAL
02451 #define COMP_ACCTL1_TSEN_FALL 0x00000020 ///< Falling edge
02452 #define COMP_ACCTL1_TSEN_RISE 0x00000040 ///< Rising edge
02453 #define COMP_ACCTL1_TSEN_BOTH 0x00000060 ///< Either edge
02454 #define COMP_ACCTL1_ISLVAL 0x00000010 ///< Interrupt Sense Level Value
02455 #define COMP_ACCTL1_ISEN_M 0x0000000C ///< Interrupt Sense
02456 #define COMP_ACCTL1_ISEN_LEVEL 0x00000000 ///< Level sense, see ISLVAL
02457 #define COMP_ACCTL1_ISEN_FALL 0x00000004 ///< Falling edge
02458 #define COMP_ACCTL1_ISEN_RISE 0x00000008 ///< Rising edge
02459 #define COMP_ACCTL1_ISEN_BOTH 0x0000000C ///< Either edge
02460 #define COMP_ACCTL1_CINV 0x00000002 ///< Comparator Output Invert
02461
02462
02466
02467 #define COMP_ACSTAT2_OVAL 0x00000002 ///< Comparator Output Value
02468
02469
02473
02474 #define COMP_ACCTL2_TOEN 0x00000800 ///< Trigger Output Enable
02475 #define COMP_ACCTL2_ASRCP_M 0x00000600 ///< Analog Source Positive
02476 #define COMP_ACCTL2_ASRCP_PIN 0x00000000 ///< Pin value of Cn+
02477 #define COMP_ACCTL2_ASRCP_PIN0 0x00000200 ///< Pin value of C0+
02478 #define COMP_ACCTL2_ASRCP_REF 0x00000400 ///< Internal voltage reference
02479
02480 #define COMP_ACCTL2_TSLVAL 0x00000080 ///< Trigger Sense Level Value
02481 #define COMP_ACCTL2_TSEN_M 0x00000060 ///< Trigger Sense
02482 #define COMP_ACCTL2_TSEN_LEVEL 0x00000000 ///< Level sense, see TSLVAL
02483 #define COMP_ACCTL2_TSEN_FALL 0x00000020 ///< Falling edge
02484 #define COMP_ACCTL2_TSEN_RISE 0x00000040 ///< Rising edge
02485 #define COMP_ACCTL2_TSEN_BOTH 0x00000060 ///< Either edge
02486 #define COMP_ACCTL2_ISLVAL 0x00000010 ///< Interrupt Sense Level Value
02487 #define COMP_ACCTL2_ISEN_M 0x0000000C ///< Interrupt Sense
02488 #define COMP_ACCTL2_ISEN_LEVEL 0x00000000 ///< Level sense, see ISLVAL
02489 #define COMP_ACCTL2_ISEN_FALL 0x00000004 ///< Falling edge
02490 #define COMP_ACCTL2_ISEN_RISE 0x00000008 ///< Rising edge
02491 #define COMP_ACCTL2_ISEN_BOTH 0x0000000C ///< Either edge
02492 #define COMP_ACCTL2_CINV 0x00000002 ///< Comparator Output Invert
02493
02494
02498
02499 #define HIB_RTCC_M 0xFFFFFFFF ///< RTC Counter
02500 #define HIB_RTCC_S 0
02501
02502
02506
02507 #define HIB_RTCM0_M 0xFFFFFFFF ///< RTC Match 0
02508 #define HIB_RTCM0_S 0
02509
02510
02514
02515 #define HIB_RTCM1_M 0xFFFFFFFF ///< RTC Match 1
02516 #define HIB_RTCM1_S 0
02517
02518
02522
02523 #define HIB_RTCLD_M 0xFFFFFFFF ///< RTC Load
02524 #define HIB_RTCLD_S 0
02525
02526
02530
02531 #define HIB_CTL_VABORT 0x00000080 ///< Power Cut Abort Enable
02532 #define HIB_CTL_CLK32EN 0x00000040 ///< Clocking Enable
02533 #define HIB_CTL_LOWBATEN 0x00000020 ///< Low Battery Monitoring Enable
02534 #define HIB_CTL_PINWEN 0x00000010 ///< External WAKE Pin Enable
02535 #define HIB_CTL_RTCWEN 0x00000008 ///< RTC Wake-up Enable
02536 #define HIB_CTL_CLKSEL 0x00000004 ///< Hibernation Module Clock Select
02537 #define HIB_CTL_HIBREQ 0x00000002 ///< Hibernation Request
02538 #define HIB_CTL_RTCEN 0x00000001 ///< RTC Timer Enable
02539
02540
02544
02545 #define HIB_IM_EXTW 0x00000008 ///< External Wake-Up Interrupt Mask
02546 #define HIB_IM_LOWBAT 0x00000004 ///< Low Battery Voltage Interrupt
02547
02548 #define HIB_IM_RTCALT1 0x00000002 ///< RTC Alert 1 Interrupt Mask
02549 #define HIB_IM_RTCALT0 0x00000001 ///< RTC Alert 0 Interrupt Mask
02550
02551
02555
02556 #define HIB_RIS_EXTW 0x00000008 ///< External Wake-Up Raw Interrupt
02557
02558 #define HIB_RIS_LOWBAT 0x00000004 ///< Low Battery Voltage Raw
02559
02560 #define HIB_RIS_RTCALT1 0x00000002 ///< RTC Alert 1 Raw Interrupt Status
02561 #define HIB_RIS_RTCALT0 0x00000001 ///< RTC Alert 0 Raw Interrupt Status
02562
02563
02567
02568 #define HIB_MIS_EXTW 0x00000008 ///< External Wake-Up Masked
02569
02570 #define HIB_MIS_LOWBAT 0x00000004 ///< Low Battery Voltage Masked
02571
02572 #define HIB_MIS_RTCALT1 0x00000002 ///< RTC Alert 1 Masked Interrupt
02573
02574 #define HIB_MIS_RTCALT0 0x00000001 ///< RTC Alert 0 Masked Interrupt
02575
02576
02577
02581
02582 #define HIB_IC_EXTW 0x00000008 ///< External Wake-Up Masked
02583
02584 #define HIB_IC_LOWBAT 0x00000004 ///< Low Battery Voltage Masked
02585
02586 #define HIB_IC_RTCALT1 0x00000002 ///< RTC Alert1 Masked Interrupt
02587
02588 #define HIB_IC_RTCALT0 0x00000001 ///< RTC Alert0 Masked Interrupt
02589
02590
02591
02595
02596 #define HIB_RTCT_TRIM_M 0x0000FFFF ///< RTC Trim Value
02597 #define HIB_RTCT_TRIM_S 0
02598
02599
02603
02604 #define HIB_DATA_RTD_M 0xFFFFFFFF ///< Hibernation Module NV Data
02605 #define HIB_DATA_RTD_S 0
02606
02607
02611
02612 #define FLASH_FMA_OFFSET_M 0x0003FFFF ///< Address Offset
02613 #define FLASH_FMA_OFFSET_S 0
02614
02615
02619
02620 #define FLASH_FMD_DATA_M 0xFFFFFFFF ///< Data Value
02621 #define FLASH_FMD_DATA_S 0
02622
02623
02627
02628 #define FLASH_FMC_WRKEY 0xA4420000 ///< FLASH write key
02629 #define FLASH_FMC_COMT 0x00000008 ///< Commit Register Value
02630 #define FLASH_FMC_MERASE 0x00000004 ///< Mass Erase Flash Memory
02631 #define FLASH_FMC_ERASE 0x00000002 ///< Erase a Page of Flash Memory
02632 #define FLASH_FMC_WRITE 0x00000001 ///< Write a Word into Flash Memory
02633
02634
02638
02639 #define FLASH_FCRIS_PRIS 0x00000002 ///< Programming Raw Interrupt Status
02640 #define FLASH_FCRIS_ARIS 0x00000001 ///< Access Raw Interrupt Status
02641
02642
02646
02647 #define FLASH_FCIM_PMASK 0x00000002 ///< Programming Interrupt Mask
02648 #define FLASH_FCIM_AMASK 0x00000001 ///< Access Interrupt Mask
02649
02650
02654
02655 #define FLASH_FCMISC_PMISC 0x00000002 ///< Programming Masked Interrupt
02656
02657 #define FLASH_FCMISC_AMISC 0x00000001 ///< Access Masked Interrupt Status
02658
02659
02660
02664
02665 #define FLASH_USECRL_M 0x000000FF ///< Microsecond Reload Value
02666 #define FLASH_USECRL_S 0
02667
02668
02672
02673 #define FLASH_USERDBG_NW 0x80000000 ///< User Debug Not Written
02674 #define FLASH_USERDBG_DATA_M 0x7FFFFFFC ///< User Data
02675 #define FLASH_USERDBG_DBG1 0x00000002 ///< Debug Control 1
02676 #define FLASH_USERDBG_DBG0 0x00000001 ///< Debug Control 0
02677 #define FLASH_USERDBG_DATA_S 2
02678
02679
02683
02684 #define FLASH_USERREG0_NW 0x80000000 ///< Not Written
02685 #define FLASH_USERREG0_DATA_M 0x7FFFFFFF ///< User Data
02686 #define FLASH_USERREG0_DATA_S 0
02687
02688
02692
02693 #define FLASH_USERREG1_NW 0x80000000 ///< Not Written
02694 #define FLASH_USERREG1_DATA_M 0x7FFFFFFF ///< User Data
02695 #define FLASH_USERREG1_DATA_S 0
02696
02697
02703
02704 #define FLASH_PROTECT_SIZE 0x00000800
02705 #define FLASH_ERASE_SIZE 0x00000400
02706
02707
02711
02712 #define NVIC_INT_TYPE_LINES_M 0x0000001F ///< Number of interrupt lines (x32)
02713 #define NVIC_INT_TYPE_LINES_S 0
02714
02715
02719
02720 #define NVIC_ST_CTRL_COUNT 0x00010000 ///< Count flag
02721 #define NVIC_ST_CTRL_CLK_SRC 0x00000004 ///< Clock Source
02722 #define NVIC_ST_CTRL_INTEN 0x00000002 ///< Interrupt enable
02723 #define NVIC_ST_CTRL_ENABLE 0x00000001 ///< Counter mode
02724
02725
02729
02730 #define NVIC_ST_RELOAD_M 0x00FFFFFF ///< Counter load value
02731 #define NVIC_ST_RELOAD_S 0
02732
02733
02738
02739 #define NVIC_ST_CURRENT_M 0x00FFFFFF ///< Counter current value
02740 #define NVIC_ST_CURRENT_S 0
02741
02742
02746
02747 #define NVIC_ST_CAL_NOREF 0x80000000 ///< No reference clock
02748 #define NVIC_ST_CAL_SKEW 0x40000000 ///< Clock skew
02749 #define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF ///< 1ms reference value
02750 #define NVIC_ST_CAL_ONEMS_S 0
02751
02752
02756
02757 #define NVIC_EN0_INT31 0x80000000 ///< Interrupt 31 enable
02758 #define NVIC_EN0_INT30 0x40000000 ///< Interrupt 30 enable
02759 #define NVIC_EN0_INT29 0x20000000 ///< Interrupt 29 enable
02760 #define NVIC_EN0_INT28 0x10000000 ///< Interrupt 28 enable
02761 #define NVIC_EN0_INT27 0x08000000 ///< Interrupt 27 enable
02762 #define NVIC_EN0_INT26 0x04000000 ///< Interrupt 26 enable
02763 #define NVIC_EN0_INT25 0x02000000 ///< Interrupt 25 enable
02764 #define NVIC_EN0_INT24 0x01000000 ///< Interrupt 24 enable
02765 #define NVIC_EN0_INT23 0x00800000 ///< Interrupt 23 enable
02766 #define NVIC_EN0_INT22 0x00400000 ///< Interrupt 22 enable
02767 #define NVIC_EN0_INT21 0x00200000 ///< Interrupt 21 enable
02768 #define NVIC_EN0_INT20 0x00100000 ///< Interrupt 20 enable
02769 #define NVIC_EN0_INT19 0x00080000 ///< Interrupt 19 enable
02770 #define NVIC_EN0_INT18 0x00040000 ///< Interrupt 18 enable
02771 #define NVIC_EN0_INT17 0x00020000 ///< Interrupt 17 enable
02772 #define NVIC_EN0_INT16 0x00010000 ///< Interrupt 16 enable
02773 #define NVIC_EN0_INT15 0x00008000 ///< Interrupt 15 enable
02774 #define NVIC_EN0_INT14 0x00004000 ///< Interrupt 14 enable
02775 #define NVIC_EN0_INT13 0x00002000 ///< Interrupt 13 enable
02776 #define NVIC_EN0_INT12 0x00001000 ///< Interrupt 12 enable
02777 #define NVIC_EN0_INT11 0x00000800 ///< Interrupt 11 enable
02778 #define NVIC_EN0_INT10 0x00000400 ///< Interrupt 10 enable
02779 #define NVIC_EN0_INT9 0x00000200 ///< Interrupt 9 enable
02780 #define NVIC_EN0_INT8 0x00000100 ///< Interrupt 8 enable
02781 #define NVIC_EN0_INT7 0x00000080 ///< Interrupt 7 enable
02782 #define NVIC_EN0_INT6 0x00000040 ///< Interrupt 6 enable
02783 #define NVIC_EN0_INT5 0x00000020 ///< Interrupt 5 enable
02784 #define NVIC_EN0_INT4 0x00000010 ///< Interrupt 4 enable
02785 #define NVIC_EN0_INT3 0x00000008 ///< Interrupt 3 enable
02786 #define NVIC_EN0_INT2 0x00000004 ///< Interrupt 2 enable
02787 #define NVIC_EN0_INT1 0x00000002 ///< Interrupt 1 enable
02788 #define NVIC_EN0_INT0 0x00000001 ///< Interrupt 0 enable
02789
02790
02794
02795 #define NVIC_EN1_INT59 0x08000000 ///< Interrupt 59 enable
02796 #define NVIC_EN1_INT58 0x04000000 ///< Interrupt 58 enable
02797 #define NVIC_EN1_INT57 0x02000000 ///< Interrupt 57 enable
02798 #define NVIC_EN1_INT56 0x01000000 ///< Interrupt 56 enable
02799 #define NVIC_EN1_INT55 0x00800000 ///< Interrupt 55 enable
02800 #define NVIC_EN1_INT54 0x00400000 ///< Interrupt 54 enable
02801 #define NVIC_EN1_INT53 0x00200000 ///< Interrupt 53 enable
02802 #define NVIC_EN1_INT52 0x00100000 ///< Interrupt 52 enable
02803 #define NVIC_EN1_INT51 0x00080000 ///< Interrupt 51 enable
02804 #define NVIC_EN1_INT50 0x00040000 ///< Interrupt 50 enable
02805 #define NVIC_EN1_INT49 0x00020000 ///< Interrupt 49 enable
02806 #define NVIC_EN1_INT48 0x00010000 ///< Interrupt 48 enable
02807 #define NVIC_EN1_INT47 0x00008000 ///< Interrupt 47 enable
02808 #define NVIC_EN1_INT46 0x00004000 ///< Interrupt 46 enable
02809 #define NVIC_EN1_INT45 0x00002000 ///< Interrupt 45 enable
02810 #define NVIC_EN1_INT44 0x00001000 ///< Interrupt 44 enable
02811 #define NVIC_EN1_INT43 0x00000800 ///< Interrupt 43 enable
02812 #define NVIC_EN1_INT42 0x00000400 ///< Interrupt 42 enable
02813 #define NVIC_EN1_INT41 0x00000200 ///< Interrupt 41 enable
02814 #define NVIC_EN1_INT40 0x00000100 ///< Interrupt 40 enable
02815 #define NVIC_EN1_INT39 0x00000080 ///< Interrupt 39 enable
02816 #define NVIC_EN1_INT38 0x00000040 ///< Interrupt 38 enable
02817 #define NVIC_EN1_INT37 0x00000020 ///< Interrupt 37 enable
02818 #define NVIC_EN1_INT36 0x00000010 ///< Interrupt 36 enable
02819 #define NVIC_EN1_INT35 0x00000008 ///< Interrupt 35 enable
02820 #define NVIC_EN1_INT34 0x00000004 ///< Interrupt 34 enable
02821 #define NVIC_EN1_INT33 0x00000002 ///< Interrupt 33 enable
02822 #define NVIC_EN1_INT32 0x00000001 ///< Interrupt 32 enable
02823
02824
02828
02829 #define NVIC_DIS0_INT31 0x80000000 ///< Interrupt 31 disable
02830 #define NVIC_DIS0_INT30 0x40000000 ///< Interrupt 30 disable
02831 #define NVIC_DIS0_INT29 0x20000000 ///< Interrupt 29 disable
02832 #define NVIC_DIS0_INT28 0x10000000 ///< Interrupt 28 disable
02833 #define NVIC_DIS0_INT27 0x08000000 ///< Interrupt 27 disable
02834 #define NVIC_DIS0_INT26 0x04000000 ///< Interrupt 26 disable
02835 #define NVIC_DIS0_INT25 0x02000000 ///< Interrupt 25 disable
02836 #define NVIC_DIS0_INT24 0x01000000 ///< Interrupt 24 disable
02837 #define NVIC_DIS0_INT23 0x00800000 ///< Interrupt 23 disable
02838 #define NVIC_DIS0_INT22 0x00400000 ///< Interrupt 22 disable
02839 #define NVIC_DIS0_INT21 0x00200000 ///< Interrupt 21 disable
02840 #define NVIC_DIS0_INT20 0x00100000 ///< Interrupt 20 disable
02841 #define NVIC_DIS0_INT19 0x00080000 ///< Interrupt 19 disable
02842 #define NVIC_DIS0_INT18 0x00040000 ///< Interrupt 18 disable
02843 #define NVIC_DIS0_INT17 0x00020000 ///< Interrupt 17 disable
02844 #define NVIC_DIS0_INT16 0x00010000 ///< Interrupt 16 disable
02845 #define NVIC_DIS0_INT15 0x00008000 ///< Interrupt 15 disable
02846 #define NVIC_DIS0_INT14 0x00004000 ///< Interrupt 14 disable
02847 #define NVIC_DIS0_INT13 0x00002000 ///< Interrupt 13 disable
02848 #define NVIC_DIS0_INT12 0x00001000 ///< Interrupt 12 disable
02849 #define NVIC_DIS0_INT11 0x00000800 ///< Interrupt 11 disable
02850 #define NVIC_DIS0_INT10 0x00000400 ///< Interrupt 10 disable
02851 #define NVIC_DIS0_INT9 0x00000200 ///< Interrupt 9 disable
02852 #define NVIC_DIS0_INT8 0x00000100 ///< Interrupt 8 disable
02853 #define NVIC_DIS0_INT7 0x00000080 ///< Interrupt 7 disable
02854 #define NVIC_DIS0_INT6 0x00000040 ///< Interrupt 6 disable
02855 #define NVIC_DIS0_INT5 0x00000020 ///< Interrupt 5 disable
02856 #define NVIC_DIS0_INT4 0x00000010 ///< Interrupt 4 disable
02857 #define NVIC_DIS0_INT3 0x00000008 ///< Interrupt 3 disable
02858 #define NVIC_DIS0_INT2 0x00000004 ///< Interrupt 2 disable
02859 #define NVIC_DIS0_INT1 0x00000002 ///< Interrupt 1 disable
02860 #define NVIC_DIS0_INT0 0x00000001 ///< Interrupt 0 disable
02861
02862
02866
02867 #define NVIC_DIS1_INT59 0x08000000 ///< Interrupt 59 disable
02868 #define NVIC_DIS1_INT58 0x04000000 ///< Interrupt 58 disable
02869 #define NVIC_DIS1_INT57 0x02000000 ///< Interrupt 57 disable
02870 #define NVIC_DIS1_INT56 0x01000000 ///< Interrupt 56 disable
02871 #define NVIC_DIS1_INT55 0x00800000 ///< Interrupt 55 disable
02872 #define NVIC_DIS1_INT54 0x00400000 ///< Interrupt 54 disable
02873 #define NVIC_DIS1_INT53 0x00200000 ///< Interrupt 53 disable
02874 #define NVIC_DIS1_INT52 0x00100000 ///< Interrupt 52 disable
02875 #define NVIC_DIS1_INT51 0x00080000 ///< Interrupt 51 disable
02876 #define NVIC_DIS1_INT50 0x00040000 ///< Interrupt 50 disable
02877 #define NVIC_DIS1_INT49 0x00020000 ///< Interrupt 49 disable
02878 #define NVIC_DIS1_INT48 0x00010000 ///< Interrupt 48 disable
02879 #define NVIC_DIS1_INT47 0x00008000 ///< Interrupt 47 disable
02880 #define NVIC_DIS1_INT46 0x00004000 ///< Interrupt 46 disable
02881 #define NVIC_DIS1_INT45 0x00002000 ///< Interrupt 45 disable
02882 #define NVIC_DIS1_INT44 0x00001000 ///< Interrupt 44 disable
02883 #define NVIC_DIS1_INT43 0x00000800 ///< Interrupt 43 disable
02884 #define NVIC_DIS1_INT42 0x00000400 ///< Interrupt 42 disable
02885 #define NVIC_DIS1_INT41 0x00000200 ///< Interrupt 41 disable
02886 #define NVIC_DIS1_INT40 0x00000100 ///< Interrupt 40 disable
02887 #define NVIC_DIS1_INT39 0x00000080 ///< Interrupt 39 disable
02888 #define NVIC_DIS1_INT38 0x00000040 ///< Interrupt 38 disable
02889 #define NVIC_DIS1_INT37 0x00000020 ///< Interrupt 37 disable
02890 #define NVIC_DIS1_INT36 0x00000010 ///< Interrupt 36 disable
02891 #define NVIC_DIS1_INT35 0x00000008 ///< Interrupt 35 disable
02892 #define NVIC_DIS1_INT34 0x00000004 ///< Interrupt 34 disable
02893 #define NVIC_DIS1_INT33 0x00000002 ///< Interrupt 33 disable
02894 #define NVIC_DIS1_INT32 0x00000001 ///< Interrupt 32 disable
02895
02896
02900
02901 #define NVIC_PEND0_INT31 0x80000000 ///< Interrupt 31 pend
02902 #define NVIC_PEND0_INT30 0x40000000 ///< Interrupt 30 pend
02903 #define NVIC_PEND0_INT29 0x20000000 ///< Interrupt 29 pend
02904 #define NVIC_PEND0_INT28 0x10000000 ///< Interrupt 28 pend
02905 #define NVIC_PEND0_INT27 0x08000000 ///< Interrupt 27 pend
02906 #define NVIC_PEND0_INT26 0x04000000 ///< Interrupt 26 pend
02907 #define NVIC_PEND0_INT25 0x02000000 ///< Interrupt 25 pend
02908 #define NVIC_PEND0_INT24 0x01000000 ///< Interrupt 24 pend
02909 #define NVIC_PEND0_INT23 0x00800000 ///< Interrupt 23 pend
02910 #define NVIC_PEND0_INT22 0x00400000 ///< Interrupt 22 pend
02911 #define NVIC_PEND0_INT21 0x00200000 ///< Interrupt 21 pend
02912 #define NVIC_PEND0_INT20 0x00100000 ///< Interrupt 20 pend
02913 #define NVIC_PEND0_INT19 0x00080000 ///< Interrupt 19 pend
02914 #define NVIC_PEND0_INT18 0x00040000 ///< Interrupt 18 pend
02915 #define NVIC_PEND0_INT17 0x00020000 ///< Interrupt 17 pend
02916 #define NVIC_PEND0_INT16 0x00010000 ///< Interrupt 16 pend
02917 #define NVIC_PEND0_INT15 0x00008000 ///< Interrupt 15 pend
02918 #define NVIC_PEND0_INT14 0x00004000 ///< Interrupt 14 pend
02919 #define NVIC_PEND0_INT13 0x00002000 ///< Interrupt 13 pend
02920 #define NVIC_PEND0_INT12 0x00001000 ///< Interrupt 12 pend
02921 #define NVIC_PEND0_INT11 0x00000800 ///< Interrupt 11 pend
02922 #define NVIC_PEND0_INT10 0x00000400 ///< Interrupt 10 pend
02923 #define NVIC_PEND0_INT9 0x00000200 ///< Interrupt 9 pend
02924 #define NVIC_PEND0_INT8 0x00000100 ///< Interrupt 8 pend
02925 #define NVIC_PEND0_INT7 0x00000080 ///< Interrupt 7 pend
02926 #define NVIC_PEND0_INT6 0x00000040 ///< Interrupt 6 pend
02927 #define NVIC_PEND0_INT5 0x00000020 ///< Interrupt 5 pend
02928 #define NVIC_PEND0_INT4 0x00000010 ///< Interrupt 4 pend
02929 #define NVIC_PEND0_INT3 0x00000008 ///< Interrupt 3 pend
02930 #define NVIC_PEND0_INT2 0x00000004 ///< Interrupt 2 pend
02931 #define NVIC_PEND0_INT1 0x00000002 ///< Interrupt 1 pend
02932 #define NVIC_PEND0_INT0 0x00000001 ///< Interrupt 0 pend
02933
02934
02938
02939 #define NVIC_PEND1_INT59 0x08000000 ///< Interrupt 59 pend
02940 #define NVIC_PEND1_INT58 0x04000000 ///< Interrupt 58 pend
02941 #define NVIC_PEND1_INT57 0x02000000 ///< Interrupt 57 pend
02942 #define NVIC_PEND1_INT56 0x01000000 ///< Interrupt 56 pend
02943 #define NVIC_PEND1_INT55 0x00800000 ///< Interrupt 55 pend
02944 #define NVIC_PEND1_INT54 0x00400000 ///< Interrupt 54 pend
02945 #define NVIC_PEND1_INT53 0x00200000 ///< Interrupt 53 pend
02946 #define NVIC_PEND1_INT52 0x00100000 ///< Interrupt 52 pend
02947 #define NVIC_PEND1_INT51 0x00080000 ///< Interrupt 51 pend
02948 #define NVIC_PEND1_INT50 0x00040000 ///< Interrupt 50 pend
02949 #define NVIC_PEND1_INT49 0x00020000 ///< Interrupt 49 pend
02950 #define NVIC_PEND1_INT48 0x00010000 ///< Interrupt 48 pend
02951 #define NVIC_PEND1_INT47 0x00008000 ///< Interrupt 47 pend
02952 #define NVIC_PEND1_INT46 0x00004000 ///< Interrupt 46 pend
02953 #define NVIC_PEND1_INT45 0x00002000 ///< Interrupt 45 pend
02954 #define NVIC_PEND1_INT44 0x00001000 ///< Interrupt 44 pend
02955 #define NVIC_PEND1_INT43 0x00000800 ///< Interrupt 43 pend
02956 #define NVIC_PEND1_INT42 0x00000400 ///< Interrupt 42 pend
02957 #define NVIC_PEND1_INT41 0x00000200 ///< Interrupt 41 pend
02958 #define NVIC_PEND1_INT40 0x00000100 ///< Interrupt 40 pend
02959 #define NVIC_PEND1_INT39 0x00000080 ///< Interrupt 39 pend
02960 #define NVIC_PEND1_INT38 0x00000040 ///< Interrupt 38 pend
02961 #define NVIC_PEND1_INT37 0x00000020 ///< Interrupt 37 pend
02962 #define NVIC_PEND1_INT36 0x00000010 ///< Interrupt 36 pend
02963 #define NVIC_PEND1_INT35 0x00000008 ///< Interrupt 35 pend
02964 #define NVIC_PEND1_INT34 0x00000004 ///< Interrupt 34 pend
02965 #define NVIC_PEND1_INT33 0x00000002 ///< Interrupt 33 pend
02966 #define NVIC_PEND1_INT32 0x00000001 ///< Interrupt 32 pend
02967
02968
02972
02973 #define NVIC_UNPEND0_INT31 0x80000000 ///< Interrupt 31 unpend
02974 #define NVIC_UNPEND0_INT30 0x40000000 ///< Interrupt 30 unpend
02975 #define NVIC_UNPEND0_INT29 0x20000000 ///< Interrupt 29 unpend
02976 #define NVIC_UNPEND0_INT28 0x10000000 ///< Interrupt 28 unpend
02977 #define NVIC_UNPEND0_INT27 0x08000000 ///< Interrupt 27 unpend
02978 #define NVIC_UNPEND0_INT26 0x04000000 ///< Interrupt 26 unpend
02979 #define NVIC_UNPEND0_INT25 0x02000000 ///< Interrupt 25 unpend
02980 #define NVIC_UNPEND0_INT24 0x01000000 ///< Interrupt 24 unpend
02981 #define NVIC_UNPEND0_INT23 0x00800000 ///< Interrupt 23 unpend
02982 #define NVIC_UNPEND0_INT22 0x00400000 ///< Interrupt 22 unpend
02983 #define NVIC_UNPEND0_INT21 0x00200000 ///< Interrupt 21 unpend
02984 #define NVIC_UNPEND0_INT20 0x00100000 ///< Interrupt 20 unpend
02985 #define NVIC_UNPEND0_INT19 0x00080000 ///< Interrupt 19 unpend
02986 #define NVIC_UNPEND0_INT18 0x00040000 ///< Interrupt 18 unpend
02987 #define NVIC_UNPEND0_INT17 0x00020000 ///< Interrupt 17 unpend
02988 #define NVIC_UNPEND0_INT16 0x00010000 ///< Interrupt 16 unpend
02989 #define NVIC_UNPEND0_INT15 0x00008000 ///< Interrupt 15 unpend
02990 #define NVIC_UNPEND0_INT14 0x00004000 ///< Interrupt 14 unpend
02991 #define NVIC_UNPEND0_INT13 0x00002000 ///< Interrupt 13 unpend
02992 #define NVIC_UNPEND0_INT12 0x00001000 ///< Interrupt 12 unpend
02993 #define NVIC_UNPEND0_INT11 0x00000800 ///< Interrupt 11 unpend
02994 #define NVIC_UNPEND0_INT10 0x00000400 ///< Interrupt 10 unpend
02995 #define NVIC_UNPEND0_INT9 0x00000200 ///< Interrupt 9 unpend
02996 #define NVIC_UNPEND0_INT8 0x00000100 ///< Interrupt 8 unpend
02997 #define NVIC_UNPEND0_INT7 0x00000080 ///< Interrupt 7 unpend
02998 #define NVIC_UNPEND0_INT6 0x00000040 ///< Interrupt 6 unpend
02999 #define NVIC_UNPEND0_INT5 0x00000020 ///< Interrupt 5 unpend
03000 #define NVIC_UNPEND0_INT4 0x00000010 ///< Interrupt 4 unpend
03001 #define NVIC_UNPEND0_INT3 0x00000008 ///< Interrupt 3 unpend
03002 #define NVIC_UNPEND0_INT2 0x00000004 ///< Interrupt 2 unpend
03003 #define NVIC_UNPEND0_INT1 0x00000002 ///< Interrupt 1 unpend
03004 #define NVIC_UNPEND0_INT0 0x00000001 ///< Interrupt 0 unpend
03005
03006
03010
03011 #define NVIC_UNPEND1_INT59 0x08000000 ///< Interrupt 59 unpend
03012 #define NVIC_UNPEND1_INT58 0x04000000 ///< Interrupt 58 unpend
03013 #define NVIC_UNPEND1_INT57 0x02000000 ///< Interrupt 57 unpend
03014 #define NVIC_UNPEND1_INT56 0x01000000 ///< Interrupt 56 unpend
03015 #define NVIC_UNPEND1_INT55 0x00800000 ///< Interrupt 55 unpend
03016 #define NVIC_UNPEND1_INT54 0x00400000 ///< Interrupt 54 unpend
03017 #define NVIC_UNPEND1_INT53 0x00200000 ///< Interrupt 53 unpend
03018 #define NVIC_UNPEND1_INT52 0x00100000 ///< Interrupt 52 unpend
03019 #define NVIC_UNPEND1_INT51 0x00080000 ///< Interrupt 51 unpend
03020 #define NVIC_UNPEND1_INT50 0x00040000 ///< Interrupt 50 unpend
03021 #define NVIC_UNPEND1_INT49 0x00020000 ///< Interrupt 49 unpend
03022 #define NVIC_UNPEND1_INT48 0x00010000 ///< Interrupt 48 unpend
03023 #define NVIC_UNPEND1_INT47 0x00008000 ///< Interrupt 47 unpend
03024 #define NVIC_UNPEND1_INT46 0x00004000 ///< Interrupt 46 unpend
03025 #define NVIC_UNPEND1_INT45 0x00002000 ///< Interrupt 45 unpend
03026 #define NVIC_UNPEND1_INT44 0x00001000 ///< Interrupt 44 unpend
03027 #define NVIC_UNPEND1_INT43 0x00000800 ///< Interrupt 43 unpend
03028 #define NVIC_UNPEND1_INT42 0x00000400 ///< Interrupt 42 unpend
03029 #define NVIC_UNPEND1_INT41 0x00000200 ///< Interrupt 41 unpend
03030 #define NVIC_UNPEND1_INT40 0x00000100 ///< Interrupt 40 unpend
03031 #define NVIC_UNPEND1_INT39 0x00000080 ///< Interrupt 39 unpend
03032 #define NVIC_UNPEND1_INT38 0x00000040 ///< Interrupt 38 unpend
03033 #define NVIC_UNPEND1_INT37 0x00000020 ///< Interrupt 37 unpend
03034 #define NVIC_UNPEND1_INT36 0x00000010 ///< Interrupt 36 unpend
03035 #define NVIC_UNPEND1_INT35 0x00000008 ///< Interrupt 35 unpend
03036 #define NVIC_UNPEND1_INT34 0x00000004 ///< Interrupt 34 unpend
03037 #define NVIC_UNPEND1_INT33 0x00000002 ///< Interrupt 33 unpend
03038 #define NVIC_UNPEND1_INT32 0x00000001 ///< Interrupt 32 unpend
03039
03040
03044
03045 #define NVIC_ACTIVE0_INT31 0x80000000 ///< Interrupt 31 active
03046 #define NVIC_ACTIVE0_INT30 0x40000000 ///< Interrupt 30 active
03047 #define NVIC_ACTIVE0_INT29 0x20000000 ///< Interrupt 29 active
03048 #define NVIC_ACTIVE0_INT28 0x10000000 ///< Interrupt 28 active
03049 #define NVIC_ACTIVE0_INT27 0x08000000 ///< Interrupt 27 active
03050 #define NVIC_ACTIVE0_INT26 0x04000000 ///< Interrupt 26 active
03051 #define NVIC_ACTIVE0_INT25 0x02000000 ///< Interrupt 25 active
03052 #define NVIC_ACTIVE0_INT24 0x01000000 ///< Interrupt 24 active
03053 #define NVIC_ACTIVE0_INT23 0x00800000 ///< Interrupt 23 active
03054 #define NVIC_ACTIVE0_INT22 0x00400000 ///< Interrupt 22 active
03055 #define NVIC_ACTIVE0_INT21 0x00200000 ///< Interrupt 21 active
03056 #define NVIC_ACTIVE0_INT20 0x00100000 ///< Interrupt 20 active
03057 #define NVIC_ACTIVE0_INT19 0x00080000 ///< Interrupt 19 active
03058 #define NVIC_ACTIVE0_INT18 0x00040000 ///< Interrupt 18 active
03059 #define NVIC_ACTIVE0_INT17 0x00020000 ///< Interrupt 17 active
03060 #define NVIC_ACTIVE0_INT16 0x00010000 ///< Interrupt 16 active
03061 #define NVIC_ACTIVE0_INT15 0x00008000 ///< Interrupt 15 active
03062 #define NVIC_ACTIVE0_INT14 0x00004000 ///< Interrupt 14 active
03063 #define NVIC_ACTIVE0_INT13 0x00002000 ///< Interrupt 13 active
03064 #define NVIC_ACTIVE0_INT12 0x00001000 ///< Interrupt 12 active
03065 #define NVIC_ACTIVE0_INT11 0x00000800 ///< Interrupt 11 active
03066 #define NVIC_ACTIVE0_INT10 0x00000400 ///< Interrupt 10 active
03067 #define NVIC_ACTIVE0_INT9 0x00000200 ///< Interrupt 9 active
03068 #define NVIC_ACTIVE0_INT8 0x00000100 ///< Interrupt 8 active
03069 #define NVIC_ACTIVE0_INT7 0x00000080 ///< Interrupt 7 active
03070 #define NVIC_ACTIVE0_INT6 0x00000040 ///< Interrupt 6 active
03071 #define NVIC_ACTIVE0_INT5 0x00000020 ///< Interrupt 5 active
03072 #define NVIC_ACTIVE0_INT4 0x00000010 ///< Interrupt 4 active
03073 #define NVIC_ACTIVE0_INT3 0x00000008 ///< Interrupt 3 active
03074 #define NVIC_ACTIVE0_INT2 0x00000004 ///< Interrupt 2 active
03075 #define NVIC_ACTIVE0_INT1 0x00000002 ///< Interrupt 1 active
03076 #define NVIC_ACTIVE0_INT0 0x00000001 ///< Interrupt 0 active
03077
03078
03082
03083 #define NVIC_ACTIVE1_INT59 0x08000000 ///< Interrupt 59 active
03084 #define NVIC_ACTIVE1_INT58 0x04000000 ///< Interrupt 58 active
03085 #define NVIC_ACTIVE1_INT57 0x02000000 ///< Interrupt 57 active
03086 #define NVIC_ACTIVE1_INT56 0x01000000 ///< Interrupt 56 active
03087 #define NVIC_ACTIVE1_INT55 0x00800000 ///< Interrupt 55 active
03088 #define NVIC_ACTIVE1_INT54 0x00400000 ///< Interrupt 54 active
03089 #define NVIC_ACTIVE1_INT53 0x00200000 ///< Interrupt 53 active
03090 #define NVIC_ACTIVE1_INT52 0x00100000 ///< Interrupt 52 active
03091 #define NVIC_ACTIVE1_INT51 0x00080000 ///< Interrupt 51 active
03092 #define NVIC_ACTIVE1_INT50 0x00040000 ///< Interrupt 50 active
03093 #define NVIC_ACTIVE1_INT49 0x00020000 ///< Interrupt 49 active
03094 #define NVIC_ACTIVE1_INT48 0x00010000 ///< Interrupt 48 active
03095 #define NVIC_ACTIVE1_INT47 0x00008000 ///< Interrupt 47 active
03096 #define NVIC_ACTIVE1_INT46 0x00004000 ///< Interrupt 46 active
03097 #define NVIC_ACTIVE1_INT45 0x00002000 ///< Interrupt 45 active
03098 #define NVIC_ACTIVE1_INT44 0x00001000 ///< Interrupt 44 active
03099 #define NVIC_ACTIVE1_INT43 0x00000800 ///< Interrupt 43 active
03100 #define NVIC_ACTIVE1_INT42 0x00000400 ///< Interrupt 42 active
03101 #define NVIC_ACTIVE1_INT41 0x00000200 ///< Interrupt 41 active
03102 #define NVIC_ACTIVE1_INT40 0x00000100 ///< Interrupt 40 active
03103 #define NVIC_ACTIVE1_INT39 0x00000080 ///< Interrupt 39 active
03104 #define NVIC_ACTIVE1_INT38 0x00000040 ///< Interrupt 38 active
03105 #define NVIC_ACTIVE1_INT37 0x00000020 ///< Interrupt 37 active
03106 #define NVIC_ACTIVE1_INT36 0x00000010 ///< Interrupt 36 active
03107 #define NVIC_ACTIVE1_INT35 0x00000008 ///< Interrupt 35 active
03108 #define NVIC_ACTIVE1_INT34 0x00000004 ///< Interrupt 34 active
03109 #define NVIC_ACTIVE1_INT33 0x00000002 ///< Interrupt 33 active
03110 #define NVIC_ACTIVE1_INT32 0x00000001 ///< Interrupt 32 active
03111
03112
03116
03117 #define NVIC_PRI0_INT3_M 0xFF000000 ///< Interrupt 3 priority mask
03118 #define NVIC_PRI0_INT2_M 0x00FF0000 ///< Interrupt 2 priority mask
03119 #define NVIC_PRI0_INT1_M 0x0000FF00 ///< Interrupt 1 priority mask
03120 #define NVIC_PRI0_INT0_M 0x000000FF ///< Interrupt 0 priority mask
03121 #define NVIC_PRI0_INT3_S 24
03122 #define NVIC_PRI0_INT2_S 16
03123 #define NVIC_PRI0_INT1_S 8
03124 #define NVIC_PRI0_INT0_S 0
03125
03126
03130
03131 #define NVIC_PRI1_INT7_M 0xFF000000 ///< Interrupt 7 priority mask
03132 #define NVIC_PRI1_INT6_M 0x00FF0000 ///< Interrupt 6 priority mask
03133 #define NVIC_PRI1_INT5_M 0x0000FF00 ///< Interrupt 5 priority mask
03134 #define NVIC_PRI1_INT4_M 0x000000FF ///< Interrupt 4 priority mask
03135 #define NVIC_PRI1_INT7_S 24
03136 #define NVIC_PRI1_INT6_S 16
03137 #define NVIC_PRI1_INT5_S 8
03138 #define NVIC_PRI1_INT4_S 0
03139
03140
03144
03145 #define NVIC_PRI2_INT11_M 0xFF000000 ///< Interrupt 11 priority mask
03146 #define NVIC_PRI2_INT10_M 0x00FF0000 ///< Interrupt 10 priority mask
03147 #define NVIC_PRI2_INT9_M 0x0000FF00 ///< Interrupt 9 priority mask
03148 #define NVIC_PRI2_INT8_M 0x000000FF ///< Interrupt 8 priority mask
03149 #define NVIC_PRI2_INT11_S 24
03150 #define NVIC_PRI2_INT10_S 16
03151 #define NVIC_PRI2_INT9_S 8
03152 #define NVIC_PRI2_INT8_S 0
03153
03154
03158
03159 #define NVIC_PRI3_INT15_M 0xFF000000 ///< Interrupt 15 priority mask
03160 #define NVIC_PRI3_INT14_M 0x00FF0000 ///< Interrupt 14 priority mask
03161 #define NVIC_PRI3_INT13_M 0x0000FF00 ///< Interrupt 13 priority mask
03162 #define NVIC_PRI3_INT12_M 0x000000FF ///< Interrupt 12 priority mask
03163 #define NVIC_PRI3_INT15_S 24
03164 #define NVIC_PRI3_INT14_S 16
03165 #define NVIC_PRI3_INT13_S 8
03166 #define NVIC_PRI3_INT12_S 0
03167
03168
03172
03173 #define NVIC_PRI4_INT19_M 0xFF000000 ///< Interrupt 19 priority mask
03174 #define NVIC_PRI4_INT18_M 0x00FF0000 ///< Interrupt 18 priority mask
03175 #define NVIC_PRI4_INT17_M 0x0000FF00 ///< Interrupt 17 priority mask
03176 #define NVIC_PRI4_INT16_M 0x000000FF ///< Interrupt 16 priority mask
03177 #define NVIC_PRI4_INT19_S 24
03178 #define NVIC_PRI4_INT18_S 16
03179 #define NVIC_PRI4_INT17_S 8
03180 #define NVIC_PRI4_INT16_S 0
03181
03182
03186
03187 #define NVIC_PRI5_INT23_M 0xFF000000 ///< Interrupt 23 priority mask
03188 #define NVIC_PRI5_INT22_M 0x00FF0000 ///< Interrupt 22 priority mask
03189 #define NVIC_PRI5_INT21_M 0x0000FF00 ///< Interrupt 21 priority mask
03190 #define NVIC_PRI5_INT20_M 0x000000FF ///< Interrupt 20 priority mask
03191 #define NVIC_PRI5_INT23_S 24
03192 #define NVIC_PRI5_INT22_S 16
03193 #define NVIC_PRI5_INT21_S 8
03194 #define NVIC_PRI5_INT20_S 0
03195
03196
03200
03201 #define NVIC_PRI6_INT27_M 0xFF000000 ///< Interrupt 27 priority mask
03202 #define NVIC_PRI6_INT26_M 0x00FF0000 ///< Interrupt 26 priority mask
03203 #define NVIC_PRI6_INT25_M 0x0000FF00 ///< Interrupt 25 priority mask
03204 #define NVIC_PRI6_INT24_M 0x000000FF ///< Interrupt 24 priority mask
03205 #define NVIC_PRI6_INT27_S 24
03206 #define NVIC_PRI6_INT26_S 16
03207 #define NVIC_PRI6_INT25_S 8
03208 #define NVIC_PRI6_INT24_S 0
03209
03210
03214
03215 #define NVIC_PRI7_INT31_M 0xFF000000 ///< Interrupt 31 priority mask
03216 #define NVIC_PRI7_INT30_M 0x00FF0000 ///< Interrupt 30 priority mask
03217 #define NVIC_PRI7_INT29_M 0x0000FF00 ///< Interrupt 29 priority mask
03218 #define NVIC_PRI7_INT28_M 0x000000FF ///< Interrupt 28 priority mask
03219 #define NVIC_PRI7_INT31_S 24
03220 #define NVIC_PRI7_INT30_S 16
03221 #define NVIC_PRI7_INT29_S 8
03222 #define NVIC_PRI7_INT28_S 0
03223
03224
03228
03229 #define NVIC_PRI8_INT35_M 0xFF000000 ///< Interrupt 35 priority mask
03230 #define NVIC_PRI8_INT34_M 0x00FF0000 ///< Interrupt 34 priority mask
03231 #define NVIC_PRI8_INT33_M 0x0000FF00 ///< Interrupt 33 priority mask
03232 #define NVIC_PRI8_INT32_M 0x000000FF ///< Interrupt 32 priority mask
03233 #define NVIC_PRI8_INT35_S 24
03234 #define NVIC_PRI8_INT34_S 16
03235 #define NVIC_PRI8_INT33_S 8
03236 #define NVIC_PRI8_INT32_S 0
03237
03238
03242
03243 #define NVIC_PRI9_INT39_M 0xFF000000 ///< Interrupt 39 priority mask
03244 #define NVIC_PRI9_INT38_M 0x00FF0000 ///< Interrupt 38 priority mask
03245 #define NVIC_PRI9_INT37_M 0x0000FF00 ///< Interrupt 37 priority mask
03246 #define NVIC_PRI9_INT36_M 0x000000FF ///< Interrupt 36 priority mask
03247 #define NVIC_PRI9_INT39_S 24
03248 #define NVIC_PRI9_INT38_S 16
03249 #define NVIC_PRI9_INT37_S 8
03250 #define NVIC_PRI9_INT36_S 0
03251
03252
03256
03257 #define NVIC_PRI10_INT43_M 0xFF000000 ///< Interrupt 43 priority mask
03258 #define NVIC_PRI10_INT42_M 0x00FF0000 ///< Interrupt 42 priority mask
03259 #define NVIC_PRI10_INT41_M 0x0000FF00 ///< Interrupt 41 priority mask
03260 #define NVIC_PRI10_INT40_M 0x000000FF ///< Interrupt 40 priority mask
03261 #define NVIC_PRI10_INT43_S 24
03262 #define NVIC_PRI10_INT42_S 16
03263 #define NVIC_PRI10_INT41_S 8
03264 #define NVIC_PRI10_INT40_S 0
03265
03266
03270
03271 #define NVIC_CPUID_IMP_M 0xFF000000 ///< Implementer
03272 #define NVIC_CPUID_VAR_M 0x00F00000 ///< Variant
03273 #define NVIC_CPUID_PARTNO_M 0x0000FFF0 ///< Processor part number
03274 #define NVIC_CPUID_REV_M 0x0000000F ///< Revision
03275
03276
03280
03281 #define NVIC_INT_CTRL_NMI_SET 0x80000000 ///< Pend a NMI
03282 #define NVIC_INT_CTRL_PEND_SV 0x10000000 ///< Pend a PendSV
03283 #define NVIC_INT_CTRL_UNPEND_SV 0x08000000 ///< Unpend a PendSV
03284 #define NVIC_INT_CTRL_PENDSTSET 0x04000000 ///< Set pending SysTick interrupt
03285 #define NVIC_INT_CTRL_PENDSTCLR 0x02000000 ///< Clear pending SysTick interrupt
03286 #define NVIC_INT_CTRL_ISR_PRE 0x00800000 ///< Debug interrupt handling
03287 #define NVIC_INT_CTRL_ISR_PEND 0x00400000 ///< Debug interrupt pending
03288 #define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 ///< Highest pending exception
03289 #define NVIC_INT_CTRL_RET_BASE 0x00000800 ///< Return to base
03290 #define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF ///< Current active exception
03291 #define NVIC_INT_CTRL_VEC_PEN_S 12
03292 #define NVIC_INT_CTRL_VEC_ACT_S 0
03293
03294
03298
03299 #define NVIC_VTABLE_BASE 0x20000000 ///< Vector table base
03300 #define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 ///< Vector table offset
03301 #define NVIC_VTABLE_OFFSET_S 8
03302
03303
03307
03308 #define NVIC_APINT_VECTKEY_M 0xFFFF0000 ///< Vector key mask
03309 #define NVIC_APINT_VECTKEY 0x05FA0000 ///< Vector key
03310 #define NVIC_APINT_ENDIANESS 0x00008000 ///< Data endianess
03311 #define NVIC_APINT_PRIGROUP_M 0x00000700 ///< Priority group
03312 #define NVIC_APINT_PRIGROUP_0_8 0x00000700 ///< Priority group 0.8 split
03313 #define NVIC_APINT_PRIGROUP_1_7 0x00000600 ///< Priority group 1.7 split
03314 #define NVIC_APINT_PRIGROUP_2_6 0x00000500 ///< Priority group 2.6 split
03315 #define NVIC_APINT_PRIGROUP_3_5 0x00000400 ///< Priority group 3.5 split
03316 #define NVIC_APINT_PRIGROUP_4_4 0x00000300 ///< Priority group 4.4 split
03317 #define NVIC_APINT_PRIGROUP_5_3 0x00000200 ///< Priority group 5.3 split
03318 #define NVIC_APINT_PRIGROUP_6_2 0x00000100 ///< Priority group 6.2 split
03319 #define NVIC_APINT_SYSRESETREQ 0x00000004 ///< System reset request
03320 #define NVIC_APINT_VECT_CLR_ACT 0x00000002 ///< Clear active NMI/fault info
03321 #define NVIC_APINT_VECT_RESET 0x00000001 ///< System reset
03322 #define NVIC_APINT_PRIGROUP_7_1 0x00000000 ///< Priority group 7.1 split
03323
03324
03328
03329 #define NVIC_SYS_CTRL_SEVONPEND 0x00000010 ///< Wakeup on pend
03330 #define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 ///< Deep sleep enable
03331 #define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 ///< Sleep on ISR exit
03332
03333
03337
03338 #define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 ///< Ignore bus fault in NMI/fault
03339 #define NVIC_CFG_CTRL_DIV0 0x00000010 ///< Trap on divide by 0
03340 #define NVIC_CFG_CTRL_UNALIGNED 0x00000008 ///< Trap on unaligned access
03341 #define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 ///< Allow deep interrupt trigger
03342 #define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 ///< Allow main interrupt trigger
03343 #define NVIC_CFG_CTRL_BASE_THR 0x00000001 ///< Thread state control
03344
03345
03349
03350 #define NVIC_SYS_PRI1_RES_M 0xFF000000 ///< Priority of reserved handler
03351 #define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 ///< Priority of usage fault handler
03352 #define NVIC_SYS_PRI1_BUS_M 0x0000FF00 ///< Priority of bus fault handler
03353 #define NVIC_SYS_PRI1_MEM_M 0x000000FF ///< Priority of mem manage handler
03354 #define NVIC_SYS_PRI1_USAGE_S 16
03355 #define NVIC_SYS_PRI1_BUS_S 8
03356 #define NVIC_SYS_PRI1_MEM_S 0
03357
03358
03362
03363 #define NVIC_SYS_PRI2_SVC_M 0xFF000000 ///< Priority of SVCall handler
03364 #define NVIC_SYS_PRI2_RES_M 0x00FFFFFF ///< Priority of reserved handlers
03365 #define NVIC_SYS_PRI2_SVC_S 24
03366
03367
03371
03372 #define NVIC_SYS_PRI3_TICK_M 0xFF000000 ///< Priority of Sys Tick handler
03373 #define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 ///< Priority of PendSV handler
03374 #define NVIC_SYS_PRI3_RES_M 0x0000FF00 ///< Priority of reserved handler
03375 #define NVIC_SYS_PRI3_DEBUG_M 0x000000FF ///< Priority of debug handler
03376 #define NVIC_SYS_PRI3_TICK_S 24
03377 #define NVIC_SYS_PRI3_PENDSV_S 16
03378 #define NVIC_SYS_PRI3_DEBUG_S 0
03379
03380
03385
03386 #define NVIC_SYS_HND_CTRL_USAGE 0x00040000 ///< Usage fault enable
03387 #define NVIC_SYS_HND_CTRL_BUS 0x00020000 ///< Bus fault enable
03388 #define NVIC_SYS_HND_CTRL_MEM 0x00010000 ///< Mem manage fault enable
03389 #define NVIC_SYS_HND_CTRL_SVC 0x00008000 ///< SVCall is pended
03390 #define NVIC_SYS_HND_CTRL_BUSP 0x00004000 ///< Bus fault is pended
03391 #define NVIC_SYS_HND_CTRL_TICK 0x00000800 ///< Sys tick is active
03392 #define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 ///< PendSV is active
03393 #define NVIC_SYS_HND_CTRL_MON 0x00000100 ///< Monitor is active
03394 #define NVIC_SYS_HND_CTRL_SVCA 0x00000080 ///< SVCall is active
03395 #define NVIC_SYS_HND_CTRL_USGA 0x00000008 ///< Usage fault is active
03396 #define NVIC_SYS_HND_CTRL_BUSA 0x00000002 ///< Bus fault is active
03397 #define NVIC_SYS_HND_CTRL_MEMA 0x00000001 ///< Mem manage is active
03398
03399
03404
03405 #define NVIC_FAULT_STAT_DIV0 0x02000000 ///< Divide by zero fault
03406 #define NVIC_FAULT_STAT_UNALIGN 0x01000000 ///< Unaligned access fault
03407 #define NVIC_FAULT_STAT_NOCP 0x00080000 ///< No coprocessor fault
03408 #define NVIC_FAULT_STAT_INVPC 0x00040000 ///< Invalid PC fault
03409 #define NVIC_FAULT_STAT_INVSTAT 0x00020000 ///< Invalid state fault
03410 #define NVIC_FAULT_STAT_UNDEF 0x00010000 ///< Undefined instruction fault
03411 #define NVIC_FAULT_STAT_BFARV 0x00008000 ///< BFAR is valid
03412 #define NVIC_FAULT_STAT_BSTKE 0x00001000 ///< Stack bus fault
03413 #define NVIC_FAULT_STAT_BUSTKE 0x00000800 ///< Unstack bus fault
03414 #define NVIC_FAULT_STAT_IMPRE 0x00000400 ///< Imprecise data bus error
03415 #define NVIC_FAULT_STAT_PRECISE 0x00000200 ///< Precise data bus error
03416 #define NVIC_FAULT_STAT_IBUS 0x00000100 ///< Instruction bus fault
03417 #define NVIC_FAULT_STAT_MMARV 0x00000080 ///< MMAR is valid
03418 #define NVIC_FAULT_STAT_MSTKE 0x00000010 ///< Stack access violation
03419 #define NVIC_FAULT_STAT_MUSTKE 0x00000008 ///< Unstack access violation
03420 #define NVIC_FAULT_STAT_DERR 0x00000002 ///< Data access violation
03421 #define NVIC_FAULT_STAT_IERR 0x00000001 ///< Instruction access violation
03422
03423
03428
03429 #define NVIC_HFAULT_STAT_DBG 0x80000000 ///< Debug event
03430 #define NVIC_HFAULT_STAT_FORCED 0x40000000 ///< Cannot execute fault handler
03431 #define NVIC_HFAULT_STAT_VECT 0x00000002 ///< Vector table read fault
03432
03433
03438
03439 #define NVIC_DEBUG_STAT_EXTRNL 0x00000010 ///< EDBGRQ asserted
03440 #define NVIC_DEBUG_STAT_VCATCH 0x00000008 ///< Vector catch
03441 #define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 ///< DWT match
03442 #define NVIC_DEBUG_STAT_BKPT 0x00000002 ///< Breakpoint instruction
03443 #define NVIC_DEBUG_STAT_HALTED 0x00000001 ///< Halt request
03444
03445
03449
03450 #define NVIC_MM_ADDR_M 0xFFFFFFFF ///< Data fault address
03451 #define NVIC_MM_ADDR_S 0
03452
03453
03458
03459 #define NVIC_FAULT_ADDR_M 0xFFFFFFFF ///< Data bus fault address
03460 #define NVIC_FAULT_ADDR_S 0
03461
03462
03466
03467 #define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 ///< Number of I regions
03468 #define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 ///< Number of D regions
03469 #define NVIC_MPU_TYPE_SEPARATE 0x00000001 ///< Separate or unified MPU
03470 #define NVIC_MPU_TYPE_IREGION_S 16
03471 #define NVIC_MPU_TYPE_DREGION_S 8
03472
03473
03477
03478 #define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 ///< MPU default region in priv mode
03479 #define NVIC_MPU_CTRL_HFNMIENA 0x00000002 ///< MPU enabled during faults
03480 #define NVIC_MPU_CTRL_ENABLE 0x00000001 ///< MPU enable
03481
03482
03487
03488 #define NVIC_MPU_NUMBER_M 0x000000FF ///< MPU region to access
03489 #define NVIC_MPU_NUMBER_S 0
03490
03491
03495
03496 #define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 ///< Base address mask
03497 #define NVIC_MPU_BASE_VALID 0x00000010 ///< Region number valid
03498 #define NVIC_MPU_BASE_REGION_M 0x0000000F ///< Region number
03499 #define NVIC_MPU_BASE_ADDR_S 8
03500 #define NVIC_MPU_BASE_REGION_S 0
03501
03502
03506
03507 #define NVIC_MPU_ATTR_M 0xFFFF0000 ///< Attributes
03508 #define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 ///< prv: no access, usr: no access
03509 #define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 ///< Bufferable
03510 #define NVIC_MPU_ATTR_CACHEABLE 0x00020000 ///< Cacheable
03511 #define NVIC_MPU_ATTR_SHAREABLE 0x00040000 ///< Shareable
03512 #define NVIC_MPU_ATTR_TEX_M 0x00380000 ///< Type extension mask
03513 #define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 ///< prv: rw, usr: none
03514 #define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 ///< prv: rw, usr: read-only
03515 #define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 ///< prv: rw, usr: rw
03516 #define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 ///< prv: ro, usr: none
03517 #define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 ///< prv: ro, usr: ro
03518 #define NVIC_MPU_ATTR_AP_M 0x07000000 ///< Access permissions mask
03519 #define NVIC_MPU_ATTR_XN 0x10000000 ///< Execute disable
03520 #define NVIC_MPU_ATTR_SRD_M 0x0000FF00 ///< Sub-region disable mask
03521 #define NVIC_MPU_ATTR_SRD_0 0x00000100 ///< Sub-region 0 disable
03522 #define NVIC_MPU_ATTR_SRD_1 0x00000200 ///< Sub-region 1 disable
03523 #define NVIC_MPU_ATTR_SRD_2 0x00000400 ///< Sub-region 2 disable
03524 #define NVIC_MPU_ATTR_SRD_3 0x00000800 ///< Sub-region 3 disable
03525 #define NVIC_MPU_ATTR_SRD_4 0x00001000 ///< Sub-region 4 disable
03526 #define NVIC_MPU_ATTR_SRD_5 0x00002000 ///< Sub-region 5 disable
03527 #define NVIC_MPU_ATTR_SRD_6 0x00004000 ///< Sub-region 6 disable
03528 #define NVIC_MPU_ATTR_SRD_7 0x00008000 ///< Sub-region 7 disable
03529 #define NVIC_MPU_ATTR_SIZE_M 0x0000003E ///< Region size mask
03530 #define NVIC_MPU_ATTR_SIZE_32B 0x00000008 ///< Region size 32 bytes
03531 #define NVIC_MPU_ATTR_SIZE_64B 0x0000000A ///< Region size 64 bytes
03532 #define NVIC_MPU_ATTR_SIZE_128B 0x0000000C ///< Region size 128 bytes
03533 #define NVIC_MPU_ATTR_SIZE_256B 0x0000000E ///< Region size 256 bytes
03534 #define NVIC_MPU_ATTR_SIZE_512B 0x00000010 ///< Region size 512 bytes
03535 #define NVIC_MPU_ATTR_SIZE_1K 0x00000012 ///< Region size 1 Kbytes
03536 #define NVIC_MPU_ATTR_SIZE_2K 0x00000014 ///< Region size 2 Kbytes
03537 #define NVIC_MPU_ATTR_SIZE_4K 0x00000016 ///< Region size 4 Kbytes
03538 #define NVIC_MPU_ATTR_SIZE_8K 0x00000018 ///< Region size 8 Kbytes
03539 #define NVIC_MPU_ATTR_SIZE_16K 0x0000001A ///< Region size 16 Kbytes
03540 #define NVIC_MPU_ATTR_SIZE_32K 0x0000001C ///< Region size 32 Kbytes
03541 #define NVIC_MPU_ATTR_SIZE_64K 0x0000001E ///< Region size 64 Kbytes
03542 #define NVIC_MPU_ATTR_SIZE_128K 0x00000020 ///< Region size 128 Kbytes
03543 #define NVIC_MPU_ATTR_SIZE_256K 0x00000022 ///< Region size 256 Kbytes
03544 #define NVIC_MPU_ATTR_SIZE_512K 0x00000024 ///< Region size 512 Kbytes
03545 #define NVIC_MPU_ATTR_SIZE_1M 0x00000026 ///< Region size 1 Mbytes
03546 #define NVIC_MPU_ATTR_SIZE_2M 0x00000028 ///< Region size 2 Mbytes
03547 #define NVIC_MPU_ATTR_SIZE_4M 0x0000002A ///< Region size 4 Mbytes
03548 #define NVIC_MPU_ATTR_SIZE_8M 0x0000002C ///< Region size 8 Mbytes
03549 #define NVIC_MPU_ATTR_SIZE_16M 0x0000002E ///< Region size 16 Mbytes
03550 #define NVIC_MPU_ATTR_SIZE_32M 0x00000030 ///< Region size 32 Mbytes
03551 #define NVIC_MPU_ATTR_SIZE_64M 0x00000032 ///< Region size 64 Mbytes
03552 #define NVIC_MPU_ATTR_SIZE_128M 0x00000034 ///< Region size 128 Mbytes
03553 #define NVIC_MPU_ATTR_SIZE_256M 0x00000036 ///< Region size 256 Mbytes
03554 #define NVIC_MPU_ATTR_SIZE_512M 0x00000038 ///< Region size 512 Mbytes
03555 #define NVIC_MPU_ATTR_SIZE_1G 0x0000003A ///< Region size 1 Gbytes
03556 #define NVIC_MPU_ATTR_SIZE_2G 0x0000003C ///< Region size 2 Gbytes
03557 #define NVIC_MPU_ATTR_SIZE_4G 0x0000003E ///< Region size 4 Gbytes
03558 #define NVIC_MPU_ATTR_ENABLE 0x00000001 ///< Region enable
03559
03560
03564
03565 #define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 ///< Debug key mask
03566 #define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 ///< Debug key
03567 #define NVIC_DBG_CTRL_S_RESET_ST \
03568 0x02000000 ///< Core has reset since last read
03569 #define NVIC_DBG_CTRL_S_RETIRE_ST \
03570 0x01000000 ///< Core has executed insruction
03571
03572 #define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 ///< Core is locked up
03573 #define NVIC_DBG_CTRL_S_SLEEP 0x00040000 ///< Core is sleeping
03574 #define NVIC_DBG_CTRL_S_HALT 0x00020000 ///< Core status on halt
03575 #define NVIC_DBG_CTRL_S_REGRDY 0x00010000 ///< Register read/write available
03576 #define NVIC_DBG_CTRL_C_SNAPSTALL \
03577 0x00000020 ///< Breaks a stalled load/store
03578 #define NVIC_DBG_CTRL_C_MASKINT 0x00000008 ///< Mask interrupts when stepping
03579 #define NVIC_DBG_CTRL_C_STEP 0x00000004 ///< Step the core
03580 #define NVIC_DBG_CTRL_C_HALT 0x00000002 ///< Halt the core
03581 #define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 ///< Enable debug
03582
03583
03587
03588 #define NVIC_DBG_XFER_REG_WNR 0x00010000 ///< Write or not read
03589 #define NVIC_DBG_XFER_REG_SEL_M 0x0000001F ///< Register
03590 #define NVIC_DBG_XFER_REG_CFBP 0x00000014 ///< Control/Fault/BasePri/PriMask
03591 #define NVIC_DBG_XFER_REG_DSP 0x00000013 ///< Deep SP
03592 #define NVIC_DBG_XFER_REG_PSP 0x00000012 ///< Process SP
03593 #define NVIC_DBG_XFER_REG_MSP 0x00000011 ///< Main SP
03594 #define NVIC_DBG_XFER_REG_FLAGS 0x00000010 ///< xPSR/Flags register
03595 #define NVIC_DBG_XFER_REG_R15 0x0000000F ///< Register R15
03596 #define NVIC_DBG_XFER_REG_R14 0x0000000E ///< Register R14
03597 #define NVIC_DBG_XFER_REG_R13 0x0000000D ///< Register R13
03598 #define NVIC_DBG_XFER_REG_R12 0x0000000C ///< Register R12
03599 #define NVIC_DBG_XFER_REG_R11 0x0000000B ///< Register R11
03600 #define NVIC_DBG_XFER_REG_R10 0x0000000A ///< Register R10
03601 #define NVIC_DBG_XFER_REG_R9 0x00000009 ///< Register R9
03602 #define NVIC_DBG_XFER_REG_R8 0x00000008 ///< Register R8
03603 #define NVIC_DBG_XFER_REG_R7 0x00000007 ///< Register R7
03604 #define NVIC_DBG_XFER_REG_R6 0x00000006 ///< Register R6
03605 #define NVIC_DBG_XFER_REG_R5 0x00000005 ///< Register R5
03606 #define NVIC_DBG_XFER_REG_R4 0x00000004 ///< Register R4
03607 #define NVIC_DBG_XFER_REG_R3 0x00000003 ///< Register R3
03608 #define NVIC_DBG_XFER_REG_R2 0x00000002 ///< Register R2
03609 #define NVIC_DBG_XFER_REG_R1 0x00000001 ///< Register R1
03610 #define NVIC_DBG_XFER_REG_R0 0x00000000 ///< Register R0
03611
03612
03616
03617 #define NVIC_DBG_DATA_M 0xFFFFFFFF ///< Data temporary cache
03618 #define NVIC_DBG_DATA_S 0
03619
03620
03624
03625 #define NVIC_DBG_INT_HARDERR 0x00000400 ///< Debug trap on hard fault
03626 #define NVIC_DBG_INT_INTERR 0x00000200 ///< Debug trap on interrupt errors
03627 #define NVIC_DBG_INT_BUSERR 0x00000100 ///< Debug trap on bus error
03628 #define NVIC_DBG_INT_STATERR 0x00000080 ///< Debug trap on usage fault state
03629 #define NVIC_DBG_INT_CHKERR 0x00000040 ///< Debug trap on usage fault check
03630 #define NVIC_DBG_INT_NOCPERR 0x00000020 ///< Debug trap on coprocessor error
03631 #define NVIC_DBG_INT_MMERR 0x00000010 ///< Debug trap on mem manage fault
03632 #define NVIC_DBG_INT_RESET 0x00000008 ///< Core reset status
03633 #define NVIC_DBG_INT_RSTPENDCLR 0x00000004 ///< Clear pending core reset
03634 #define NVIC_DBG_INT_RSTPENDING 0x00000002 ///< Core reset is pending
03635 #define NVIC_DBG_INT_RSTVCATCH 0x00000001 ///< Reset vector catch
03636
03637
03641
03642 #define NVIC_SW_TRIG_INTID_M 0x000003FF ///< Interrupt to trigger
03643 #define NVIC_SW_TRIG_INTID_S 0
03644
03645
03649 #ifndef DEPRECATED
03650
03654
03655 #define WATCHDOG_LOAD_R (*((reg32_t *)0x40000000))
03656 #define WATCHDOG_VALUE_R (*((reg32_t *)0x40000004))
03657 #define WATCHDOG_CTL_R (*((reg32_t *)0x40000008))
03658 #define WATCHDOG_ICR_R (*((reg32_t *)0x4000000C))
03659 #define WATCHDOG_RIS_R (*((reg32_t *)0x40000010))
03660 #define WATCHDOG_MIS_R (*((reg32_t *)0x40000014))
03661 #define WATCHDOG_TEST_R (*((reg32_t *)0x40000418))
03662 #define WATCHDOG_LOCK_R (*((reg32_t *)0x40000C00))
03663
03664
03668
03669 #define I2C_SICR_IC 0x00000001 ///< Clear Interrupt
03670
03671
03675
03676 #define I2C_SMIS_MIS 0x00000001 ///< Masked Interrupt Status
03677
03678
03682
03683 #define I2C_SRIS_RIS 0x00000001 ///< Raw Interrupt Status
03684
03685
03689
03690 #define I2C_SIMR_IM 0x00000001 ///< Interrupt Mask
03691
03692
03697
03698 #define ADC_TMLB_CNT_M 0x000003C0 ///< Continuous Sample Counter
03699 #define ADC_TMLB_CONT 0x00000020 ///< Continuation Sample Indicator
03700 #define ADC_TMLB_DIFF 0x00000010 ///< Differential Sample Indicator
03701 #define ADC_TMLB_TS 0x00000008 ///< Temp Sensor Sample Indicator
03702 #define ADC_TMLB_MUX_M 0x00000007 ///< Analog Input Indicator
03703 #define ADC_TMLB_CNT_S 6 ///< Sample counter shift
03704 #define ADC_TMLB_MUX_S 0 ///< Input channel number shift
03705
03706
03710
03711 #define ADC_ACTSS_R (*((reg32_t *)0x40038000))
03712 #define ADC_RIS_R (*((reg32_t *)0x40038004))
03713 #define ADC_IM_R (*((reg32_t *)0x40038008))
03714 #define ADC_ISC_R (*((reg32_t *)0x4003800C))
03715 #define ADC_OSTAT_R (*((reg32_t *)0x40038010))
03716 #define ADC_EMUX_R (*((reg32_t *)0x40038014))
03717 #define ADC_USTAT_R (*((reg32_t *)0x40038018))
03718 #define ADC_SSPRI_R (*((reg32_t *)0x40038020))
03719 #define ADC_PSSI_R (*((reg32_t *)0x40038028))
03720 #define ADC_SAC_R (*((reg32_t *)0x40038030))
03721 #define ADC_SSMUX0_R (*((reg32_t *)0x40038040))
03722 #define ADC_SSCTL0_R (*((reg32_t *)0x40038044))
03723 #define ADC_SSFIFO0_R (*((reg32_t *)0x40038048))
03724 #define ADC_SSFSTAT0_R (*((reg32_t *)0x4003804C))
03725 #define ADC_SSMUX1_R (*((reg32_t *)0x40038060))
03726 #define ADC_SSCTL1_R (*((reg32_t *)0x40038064))
03727 #define ADC_SSFIFO1_R (*((reg32_t *)0x40038068))
03728 #define ADC_SSFSTAT1_R (*((reg32_t *)0x4003806C))
03729 #define ADC_SSMUX2_R (*((reg32_t *)0x40038080))
03730 #define ADC_SSCTL2_R (*((reg32_t *)0x40038084))
03731 #define ADC_SSFIFO2_R (*((reg32_t *)0x40038088))
03732 #define ADC_SSFSTAT2_R (*((reg32_t *)0x4003808C))
03733 #define ADC_SSMUX3_R (*((reg32_t *)0x400380A0))
03734 #define ADC_SSCTL3_R (*((reg32_t *)0x400380A4))
03735 #define ADC_SSFIFO3_R (*((reg32_t *)0x400380A8))
03736 #define ADC_SSFSTAT3_R (*((reg32_t *)0x400380AC))
03737 #define ADC_TMLB_R (*((reg32_t *)0x40038100))
03738
03739
03743
03744 #define FLASH_FMC_WRKEY_M 0xFFFF0000 ///< Flash Memory Write Key
03745 #define FLASH_FMC_WRKEY_S 16
03746
03747
03751
03752 #define SYSCTL_DID1_PKG_28SOIC 0x00000000 ///< SOIC package
03753 #define SYSCTL_DID1_PKG_48QFP 0x00000008 ///< QFP package
03754
03755
03759
03760 #define NVIC_MPU_R (*((reg32_t *)0xE000ED9C))
03761
03762
03763 #endif
03764
03765 #endif
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