lpc23xx.h

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00001 
00038 #ifndef LPC23XX_H
00039 #define LPC23XX_H
00040 
00041 #include <cfg/compiler.h>
00042 
00043 /* Vectored Interrupt Controller (VIC) */
00044 #define VIC_BASE_ADDR   0xFFFFF000
00045 #define VICIRQStatus   (*(reg32_t *)(VIC_BASE_ADDR + 0x000))
00046 #define VICFIQStatus   (*(reg32_t *)(VIC_BASE_ADDR + 0x004))
00047 #define VICRawIntr     (*(reg32_t *)(VIC_BASE_ADDR + 0x008))
00048 #define VICIntSelect   (*(reg32_t *)(VIC_BASE_ADDR + 0x00C))
00049 #define VICIntEnable   (*(reg32_t *)(VIC_BASE_ADDR + 0x010))
00050 #define VICIntEnClr    (*(reg32_t *)(VIC_BASE_ADDR + 0x014))
00051 #define VICSoftInt     (*(reg32_t *)(VIC_BASE_ADDR + 0x018))
00052 #define VICSoftIntClr  (*(reg32_t *)(VIC_BASE_ADDR + 0x01C))
00053 #define VICProtection  (*(reg32_t *)(VIC_BASE_ADDR + 0x020))
00054 #define VICSWPrioMask  (*(reg32_t *)(VIC_BASE_ADDR + 0x024))
00055 
00056 #define VICVectAddr0   (*(reg32_t *)(VIC_BASE_ADDR + 0x100))
00057 #define VICVectAddr1   (*(reg32_t *)(VIC_BASE_ADDR + 0x104))
00058 #define VICVectAddr2   (*(reg32_t *)(VIC_BASE_ADDR + 0x108))
00059 #define VICVectAddr3   (*(reg32_t *)(VIC_BASE_ADDR + 0x10C))
00060 #define VICVectAddr4   (*(reg32_t *)(VIC_BASE_ADDR + 0x110))
00061 #define VICVectAddr5   (*(reg32_t *)(VIC_BASE_ADDR + 0x114))
00062 #define VICVectAddr6   (*(reg32_t *)(VIC_BASE_ADDR + 0x118))
00063 #define VICVectAddr7   (*(reg32_t *)(VIC_BASE_ADDR + 0x11C))
00064 #define VICVectAddr8   (*(reg32_t *)(VIC_BASE_ADDR + 0x120))
00065 #define VICVectAddr9   (*(reg32_t *)(VIC_BASE_ADDR + 0x124))
00066 #define VICVectAddr10  (*(reg32_t *)(VIC_BASE_ADDR + 0x128))
00067 #define VICVectAddr11  (*(reg32_t *)(VIC_BASE_ADDR + 0x12C))
00068 #define VICVectAddr12  (*(reg32_t *)(VIC_BASE_ADDR + 0x130))
00069 #define VICVectAddr13  (*(reg32_t *)(VIC_BASE_ADDR + 0x134))
00070 #define VICVectAddr14  (*(reg32_t *)(VIC_BASE_ADDR + 0x138))
00071 #define VICVectAddr15  (*(reg32_t *)(VIC_BASE_ADDR + 0x13C))
00072 #define VICVectAddr16  (*(reg32_t *)(VIC_BASE_ADDR + 0x140))
00073 #define VICVectAddr17  (*(reg32_t *)(VIC_BASE_ADDR + 0x144))
00074 #define VICVectAddr18  (*(reg32_t *)(VIC_BASE_ADDR + 0x148))
00075 #define VICVectAddr19  (*(reg32_t *)(VIC_BASE_ADDR + 0x14C))
00076 #define VICVectAddr20  (*(reg32_t *)(VIC_BASE_ADDR + 0x150))
00077 #define VICVectAddr21  (*(reg32_t *)(VIC_BASE_ADDR + 0x154))
00078 #define VICVectAddr22  (*(reg32_t *)(VIC_BASE_ADDR + 0x158))
00079 #define VICVectAddr23  (*(reg32_t *)(VIC_BASE_ADDR + 0x15C))
00080 #define VICVectAddr24  (*(reg32_t *)(VIC_BASE_ADDR + 0x160))
00081 #define VICVectAddr25  (*(reg32_t *)(VIC_BASE_ADDR + 0x164))
00082 #define VICVectAddr26  (*(reg32_t *)(VIC_BASE_ADDR + 0x168))
00083 #define VICVectAddr27  (*(reg32_t *)(VIC_BASE_ADDR + 0x16C))
00084 #define VICVectAddr28  (*(reg32_t *)(VIC_BASE_ADDR + 0x170))
00085 #define VICVectAddr29  (*(reg32_t *)(VIC_BASE_ADDR + 0x174))
00086 #define VICVectAddr30  (*(reg32_t *)(VIC_BASE_ADDR + 0x178))
00087 #define VICVectAddr31  (*(reg32_t *)(VIC_BASE_ADDR + 0x17C))
00088 
00089 /* The name convention below is from previous LPC2000 family MCUs, in LPC23xx/24xx,
00090 these registers are known as "VICVectPriority(x)". */
00091 #define VICVectCntl0   (*(reg32_t *)(VIC_BASE_ADDR + 0x200))
00092 #define VICVectCntl1   (*(reg32_t *)(VIC_BASE_ADDR + 0x204))
00093 #define VICVectCntl2   (*(reg32_t *)(VIC_BASE_ADDR + 0x208))
00094 #define VICVectCntl3   (*(reg32_t *)(VIC_BASE_ADDR + 0x20C))
00095 #define VICVectCntl4   (*(reg32_t *)(VIC_BASE_ADDR + 0x210))
00096 #define VICVectCntl5   (*(reg32_t *)(VIC_BASE_ADDR + 0x214))
00097 #define VICVectCntl6   (*(reg32_t *)(VIC_BASE_ADDR + 0x218))
00098 #define VICVectCntl7   (*(reg32_t *)(VIC_BASE_ADDR + 0x21C))
00099 #define VICVectCntl8   (*(reg32_t *)(VIC_BASE_ADDR + 0x220))
00100 #define VICVectCntl9   (*(reg32_t *)(VIC_BASE_ADDR + 0x224))
00101 #define VICVectCntl10  (*(reg32_t *)(VIC_BASE_ADDR + 0x228))
00102 #define VICVectCntl11  (*(reg32_t *)(VIC_BASE_ADDR + 0x22C))
00103 #define VICVectCntl12  (*(reg32_t *)(VIC_BASE_ADDR + 0x230))
00104 #define VICVectCntl13  (*(reg32_t *)(VIC_BASE_ADDR + 0x234))
00105 #define VICVectCntl14  (*(reg32_t *)(VIC_BASE_ADDR + 0x238))
00106 #define VICVectCntl15  (*(reg32_t *)(VIC_BASE_ADDR + 0x23C))
00107 #define VICVectCntl16  (*(reg32_t *)(VIC_BASE_ADDR + 0x240))
00108 #define VICVectCntl17  (*(reg32_t *)(VIC_BASE_ADDR + 0x244))
00109 #define VICVectCntl18  (*(reg32_t *)(VIC_BASE_ADDR + 0x248))
00110 #define VICVectCntl19  (*(reg32_t *)(VIC_BASE_ADDR + 0x24C))
00111 #define VICVectCntl20  (*(reg32_t *)(VIC_BASE_ADDR + 0x250))
00112 #define VICVectCntl21  (*(reg32_t *)(VIC_BASE_ADDR + 0x254))
00113 #define VICVectCntl22  (*(reg32_t *)(VIC_BASE_ADDR + 0x258))
00114 #define VICVectCntl23  (*(reg32_t *)(VIC_BASE_ADDR + 0x25C))
00115 #define VICVectCntl24  (*(reg32_t *)(VIC_BASE_ADDR + 0x260))
00116 #define VICVectCntl25  (*(reg32_t *)(VIC_BASE_ADDR + 0x264))
00117 #define VICVectCntl26  (*(reg32_t *)(VIC_BASE_ADDR + 0x268))
00118 #define VICVectCntl27  (*(reg32_t *)(VIC_BASE_ADDR + 0x26C))
00119 #define VICVectCntl28  (*(reg32_t *)(VIC_BASE_ADDR + 0x270))
00120 #define VICVectCntl29  (*(reg32_t *)(VIC_BASE_ADDR + 0x274))
00121 #define VICVectCntl30  (*(reg32_t *)(VIC_BASE_ADDR + 0x278))
00122 #define VICVectCntl31  (*(reg32_t *)(VIC_BASE_ADDR + 0x27C))
00123 
00124 #define VICVectAddr    (*(reg32_t *)(VIC_BASE_ADDR + 0xF00))
00125 
00126 
00127 /* Pin Connect Block */
00128 #define PINSEL_BASE_ADDR    0xE002C000
00129 #define PINSEL0        (*(reg32_t *)(PINSEL_BASE_ADDR + 0x00))
00130 #define PINSEL1        (*(reg32_t *)(PINSEL_BASE_ADDR + 0x04))
00131 #define PINSEL2        (*(reg32_t *)(PINSEL_BASE_ADDR + 0x08))
00132 #define PINSEL3        (*(reg32_t *)(PINSEL_BASE_ADDR + 0x0C))
00133 #define PINSEL4        (*(reg32_t *)(PINSEL_BASE_ADDR + 0x10))
00134 #define PINSEL5        (*(reg32_t *)(PINSEL_BASE_ADDR + 0x14))
00135 #define PINSEL6        (*(reg32_t *)(PINSEL_BASE_ADDR + 0x18))
00136 #define PINSEL7        (*(reg32_t *)(PINSEL_BASE_ADDR + 0x1C))
00137 #define PINSEL8        (*(reg32_t *)(PINSEL_BASE_ADDR + 0x20))
00138 #define PINSEL9        (*(reg32_t *)(PINSEL_BASE_ADDR + 0x24))
00139 #define PINSEL10       (*(reg32_t *)(PINSEL_BASE_ADDR + 0x28))
00140 
00141 #define PINMODE0        (*(reg32_t *)(PINSEL_BASE_ADDR + 0x40))
00142 #define PINMODE1        (*(reg32_t *)(PINSEL_BASE_ADDR + 0x44))
00143 #define PINMODE2        (*(reg32_t *)(PINSEL_BASE_ADDR + 0x48))
00144 #define PINMODE3        (*(reg32_t *)(PINSEL_BASE_ADDR + 0x4C))
00145 #define PINMODE4        (*(reg32_t *)(PINSEL_BASE_ADDR + 0x50))
00146 #define PINMODE5        (*(reg32_t *)(PINSEL_BASE_ADDR + 0x54))
00147 #define PINMODE6        (*(reg32_t *)(PINSEL_BASE_ADDR + 0x58))
00148 #define PINMODE7        (*(reg32_t *)(PINSEL_BASE_ADDR + 0x5C))
00149 #define PINMODE8        (*(reg32_t *)(PINSEL_BASE_ADDR + 0x60))
00150 #define PINMODE9        (*(reg32_t *)(PINSEL_BASE_ADDR + 0x64))
00151 
00152 /* General Purpose Input/Output (GPIO) */
00153 #define GPIO_BASE_ADDR      0xE0028000
00154 #define IOPIN0         (*(reg32_t *)(GPIO_BASE_ADDR + 0x00))
00155 #define IOSET0         (*(reg32_t *)(GPIO_BASE_ADDR + 0x04))
00156 #define IODIR0         (*(reg32_t *)(GPIO_BASE_ADDR + 0x08))
00157 #define IOCLR0         (*(reg32_t *)(GPIO_BASE_ADDR + 0x0C))
00158 #define IOPIN1         (*(reg32_t *)(GPIO_BASE_ADDR + 0x10))
00159 #define IOSET1         (*(reg32_t *)(GPIO_BASE_ADDR + 0x14))
00160 #define IODIR1         (*(reg32_t *)(GPIO_BASE_ADDR + 0x18))
00161 #define IOCLR1         (*(reg32_t *)(GPIO_BASE_ADDR + 0x1C))
00162 
00163 /* GPIO Interrupt Registers */
00164 #define IO0_INT_EN_R    (*(reg32_t *)(GPIO_BASE_ADDR + 0x90)) 
00165 #define IO0_INT_EN_F    (*(reg32_t *)(GPIO_BASE_ADDR + 0x94))
00166 #define IO0_INT_STAT_R  (*(reg32_t *)(GPIO_BASE_ADDR + 0x84))
00167 #define IO0_INT_STAT_F  (*(reg32_t *)(GPIO_BASE_ADDR + 0x88))
00168 #define IO0_INT_CLR     (*(reg32_t *)(GPIO_BASE_ADDR + 0x8C))
00169 
00170 #define IO2_INT_EN_R    (*(reg32_t *)(GPIO_BASE_ADDR + 0xB0)) 
00171 #define IO2_INT_EN_F    (*(reg32_t *)(GPIO_BASE_ADDR + 0xB4))
00172 #define IO2_INT_STAT_R  (*(reg32_t *)(GPIO_BASE_ADDR + 0xA4))
00173 #define IO2_INT_STAT_F  (*(reg32_t *)(GPIO_BASE_ADDR + 0xA8))
00174 #define IO2_INT_CLR     (*(reg32_t *)(GPIO_BASE_ADDR + 0xAC))
00175 
00176 #define IO_INT_STAT     (*(reg32_t *)(GPIO_BASE_ADDR + 0x80))
00177 
00178 #define PARTCFG_BASE_ADDR       0x3FFF8000
00179 #define PARTCFG        (*(reg32_t *)(PARTCFG_BASE_ADDR + 0x00)) 
00180 
00181 /* Fast I/O setup */
00182 #define FIO_BASE_ADDR       0x3FFFC000
00183 #define FIO0DIR        (*(reg32_t *)(FIO_BASE_ADDR + 0x00)) 
00184 #define FIO0MASK       (*(reg32_t *)(FIO_BASE_ADDR + 0x10))
00185 #define FIO0PIN        (*(reg32_t *)(FIO_BASE_ADDR + 0x14))
00186 #define FIO0SET        (*(reg32_t *)(FIO_BASE_ADDR + 0x18))
00187 #define FIO0CLR        (*(reg32_t *)(FIO_BASE_ADDR + 0x1C))
00188 
00189 #define FIO1DIR        (*(reg32_t *)(FIO_BASE_ADDR + 0x20)) 
00190 #define FIO1MASK       (*(reg32_t *)(FIO_BASE_ADDR + 0x30))
00191 #define FIO1PIN        (*(reg32_t *)(FIO_BASE_ADDR + 0x34))
00192 #define FIO1SET        (*(reg32_t *)(FIO_BASE_ADDR + 0x38))
00193 #define FIO1CLR        (*(reg32_t *)(FIO_BASE_ADDR + 0x3C))
00194 
00195 #define FIO2DIR        (*(reg32_t *)(FIO_BASE_ADDR + 0x40)) 
00196 #define FIO2MASK       (*(reg32_t *)(FIO_BASE_ADDR + 0x50))
00197 #define FIO2PIN        (*(reg32_t *)(FIO_BASE_ADDR + 0x54))
00198 #define FIO2SET        (*(reg32_t *)(FIO_BASE_ADDR + 0x58))
00199 #define FIO2CLR        (*(reg32_t *)(FIO_BASE_ADDR + 0x5C))
00200 
00201 #define FIO3DIR        (*(reg32_t *)(FIO_BASE_ADDR + 0x60)) 
00202 #define FIO3MASK       (*(reg32_t *)(FIO_BASE_ADDR + 0x70))
00203 #define FIO3PIN        (*(reg32_t *)(FIO_BASE_ADDR + 0x74))
00204 #define FIO3SET        (*(reg32_t *)(FIO_BASE_ADDR + 0x78))
00205 #define FIO3CLR        (*(reg32_t *)(FIO_BASE_ADDR + 0x7C))
00206 
00207 #define FIO4DIR        (*(reg32_t *)(FIO_BASE_ADDR + 0x80)) 
00208 #define FIO4MASK       (*(reg32_t *)(FIO_BASE_ADDR + 0x90))
00209 #define FIO4PIN        (*(reg32_t *)(FIO_BASE_ADDR + 0x94))
00210 #define FIO4SET        (*(reg32_t *)(FIO_BASE_ADDR + 0x98))
00211 #define FIO4CLR        (*(reg32_t *)(FIO_BASE_ADDR + 0x9C))
00212 
00213 /* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
00214 #define FIO0DIR0       (*(reg8_t *)(FIO_BASE_ADDR + 0x00)) 
00215 #define FIO1DIR0       (*(reg8_t *)(FIO_BASE_ADDR + 0x20)) 
00216 #define FIO2DIR0       (*(reg8_t *)(FIO_BASE_ADDR + 0x40)) 
00217 #define FIO3DIR0       (*(reg8_t *)(FIO_BASE_ADDR + 0x60)) 
00218 #define FIO4DIR0       (*(reg8_t *)(FIO_BASE_ADDR + 0x80)) 
00219 
00220 #define FIO0DIR1       (*(reg8_t *)(FIO_BASE_ADDR + 0x01)) 
00221 #define FIO1DIR1       (*(reg8_t *)(FIO_BASE_ADDR + 0x21)) 
00222 #define FIO2DIR1       (*(reg8_t *)(FIO_BASE_ADDR + 0x41)) 
00223 #define FIO3DIR1       (*(reg8_t *)(FIO_BASE_ADDR + 0x61)) 
00224 #define FIO4DIR1       (*(reg8_t *)(FIO_BASE_ADDR + 0x81)) 
00225 
00226 #define FIO0DIR2       (*(reg8_t *)(FIO_BASE_ADDR + 0x02)) 
00227 #define FIO1DIR2       (*(reg8_t *)(FIO_BASE_ADDR + 0x22)) 
00228 #define FIO2DIR2       (*(reg8_t *)(FIO_BASE_ADDR + 0x42)) 
00229 #define FIO3DIR2       (*(reg8_t *)(FIO_BASE_ADDR + 0x62)) 
00230 #define FIO4DIR2       (*(reg8_t *)(FIO_BASE_ADDR + 0x82)) 
00231 
00232 #define FIO0DIR3       (*(reg8_t *)(FIO_BASE_ADDR + 0x03)) 
00233 #define FIO1DIR3       (*(reg8_t *)(FIO_BASE_ADDR + 0x23)) 
00234 #define FIO2DIR3       (*(reg8_t *)(FIO_BASE_ADDR + 0x43)) 
00235 #define FIO3DIR3       (*(reg8_t *)(FIO_BASE_ADDR + 0x63)) 
00236 #define FIO4DIR3       (*(reg8_t *)(FIO_BASE_ADDR + 0x83)) 
00237 
00238 #define FIO0DIRL       (*(reg16_t *)(FIO_BASE_ADDR + 0x00)) 
00239 #define FIO1DIRL       (*(reg16_t *)(FIO_BASE_ADDR + 0x20)) 
00240 #define FIO2DIRL       (*(reg16_t *)(FIO_BASE_ADDR + 0x40)) 
00241 #define FIO3DIRL       (*(reg16_t *)(FIO_BASE_ADDR + 0x60)) 
00242 #define FIO4DIRL       (*(reg16_t *)(FIO_BASE_ADDR + 0x80)) 
00243 
00244 #define FIO0DIRU       (*(reg16_t *)(FIO_BASE_ADDR + 0x02)) 
00245 #define FIO1DIRU       (*(reg16_t *)(FIO_BASE_ADDR + 0x22)) 
00246 #define FIO2DIRU       (*(reg16_t *)(FIO_BASE_ADDR + 0x42)) 
00247 #define FIO3DIRU       (*(reg16_t *)(FIO_BASE_ADDR + 0x62)) 
00248 #define FIO4DIRU       (*(reg16_t *)(FIO_BASE_ADDR + 0x82)) 
00249 
00250 #define FIO0MASK0      (*(reg8_t *)(FIO_BASE_ADDR + 0x10)) 
00251 #define FIO1MASK0      (*(reg8_t *)(FIO_BASE_ADDR + 0x30)) 
00252 #define FIO2MASK0      (*(reg8_t *)(FIO_BASE_ADDR + 0x50)) 
00253 #define FIO3MASK0      (*(reg8_t *)(FIO_BASE_ADDR + 0x70)) 
00254 #define FIO4MASK0      (*(reg8_t *)(FIO_BASE_ADDR + 0x90)) 
00255 
00256 #define FIO0MASK1      (*(reg8_t *)(FIO_BASE_ADDR + 0x11)) 
00257 #define FIO1MASK1      (*(reg8_t *)(FIO_BASE_ADDR + 0x21)) 
00258 #define FIO2MASK1      (*(reg8_t *)(FIO_BASE_ADDR + 0x51)) 
00259 #define FIO3MASK1      (*(reg8_t *)(FIO_BASE_ADDR + 0x71)) 
00260 #define FIO4MASK1      (*(reg8_t *)(FIO_BASE_ADDR + 0x91)) 
00261 
00262 #define FIO0MASK2      (*(reg8_t *)(FIO_BASE_ADDR + 0x12)) 
00263 #define FIO1MASK2      (*(reg8_t *)(FIO_BASE_ADDR + 0x32)) 
00264 #define FIO2MASK2      (*(reg8_t *)(FIO_BASE_ADDR + 0x52)) 
00265 #define FIO3MASK2      (*(reg8_t *)(FIO_BASE_ADDR + 0x72)) 
00266 #define FIO4MASK2      (*(reg8_t *)(FIO_BASE_ADDR + 0x92)) 
00267 
00268 #define FIO0MASK3      (*(reg8_t *)(FIO_BASE_ADDR + 0x13)) 
00269 #define FIO1MASK3      (*(reg8_t *)(FIO_BASE_ADDR + 0x33)) 
00270 #define FIO2MASK3      (*(reg8_t *)(FIO_BASE_ADDR + 0x53)) 
00271 #define FIO3MASK3      (*(reg8_t *)(FIO_BASE_ADDR + 0x73)) 
00272 #define FIO4MASK3      (*(reg8_t *)(FIO_BASE_ADDR + 0x93)) 
00273 
00274 #define FIO0MASKL      (*(reg16_t *)(FIO_BASE_ADDR + 0x10)) 
00275 #define FIO1MASKL      (*(reg16_t *)(FIO_BASE_ADDR + 0x30)) 
00276 #define FIO2MASKL      (*(reg16_t *)(FIO_BASE_ADDR + 0x50)) 
00277 #define FIO3MASKL      (*(reg16_t *)(FIO_BASE_ADDR + 0x70)) 
00278 #define FIO4MASKL      (*(reg16_t *)(FIO_BASE_ADDR + 0x90)) 
00279 
00280 #define FIO0MASKU      (*(reg16_t *)(FIO_BASE_ADDR + 0x12)) 
00281 #define FIO1MASKU      (*(reg16_t *)(FIO_BASE_ADDR + 0x32)) 
00282 #define FIO2MASKU      (*(reg16_t *)(FIO_BASE_ADDR + 0x52)) 
00283 #define FIO3MASKU      (*(reg16_t *)(FIO_BASE_ADDR + 0x72)) 
00284 #define FIO4MASKU      (*(reg16_t *)(FIO_BASE_ADDR + 0x92)) 
00285 
00286 #define FIO0PIN0       (*(reg8_t *)(FIO_BASE_ADDR + 0x14)) 
00287 #define FIO1PIN0       (*(reg8_t *)(FIO_BASE_ADDR + 0x34)) 
00288 #define FIO2PIN0       (*(reg8_t *)(FIO_BASE_ADDR + 0x54)) 
00289 #define FIO3PIN0       (*(reg8_t *)(FIO_BASE_ADDR + 0x74)) 
00290 #define FIO4PIN0       (*(reg8_t *)(FIO_BASE_ADDR + 0x94)) 
00291 
00292 #define FIO0PIN1       (*(reg8_t *)(FIO_BASE_ADDR + 0x15)) 
00293 #define FIO1PIN1       (*(reg8_t *)(FIO_BASE_ADDR + 0x25)) 
00294 #define FIO2PIN1       (*(reg8_t *)(FIO_BASE_ADDR + 0x55)) 
00295 #define FIO3PIN1       (*(reg8_t *)(FIO_BASE_ADDR + 0x75)) 
00296 #define FIO4PIN1       (*(reg8_t *)(FIO_BASE_ADDR + 0x95)) 
00297 
00298 #define FIO0PIN2       (*(reg8_t *)(FIO_BASE_ADDR + 0x16)) 
00299 #define FIO1PIN2       (*(reg8_t *)(FIO_BASE_ADDR + 0x36)) 
00300 #define FIO2PIN2       (*(reg8_t *)(FIO_BASE_ADDR + 0x56)) 
00301 #define FIO3PIN2       (*(reg8_t *)(FIO_BASE_ADDR + 0x76)) 
00302 #define FIO4PIN2       (*(reg8_t *)(FIO_BASE_ADDR + 0x96)) 
00303 
00304 #define FIO0PIN3       (*(reg8_t *)(FIO_BASE_ADDR + 0x17)) 
00305 #define FIO1PIN3       (*(reg8_t *)(FIO_BASE_ADDR + 0x37)) 
00306 #define FIO2PIN3       (*(reg8_t *)(FIO_BASE_ADDR + 0x57)) 
00307 #define FIO3PIN3       (*(reg8_t *)(FIO_BASE_ADDR + 0x77)) 
00308 #define FIO4PIN3       (*(reg8_t *)(FIO_BASE_ADDR + 0x97)) 
00309 
00310 #define FIO0PINL       (*(reg16_t *)(FIO_BASE_ADDR + 0x14)) 
00311 #define FIO1PINL       (*(reg16_t *)(FIO_BASE_ADDR + 0x34)) 
00312 #define FIO2PINL       (*(reg16_t *)(FIO_BASE_ADDR + 0x54)) 
00313 #define FIO3PINL       (*(reg16_t *)(FIO_BASE_ADDR + 0x74)) 
00314 #define FIO4PINL       (*(reg16_t *)(FIO_BASE_ADDR + 0x94)) 
00315 
00316 #define FIO0PINU       (*(reg16_t *)(FIO_BASE_ADDR + 0x16)) 
00317 #define FIO1PINU       (*(reg16_t *)(FIO_BASE_ADDR + 0x36)) 
00318 #define FIO2PINU       (*(reg16_t *)(FIO_BASE_ADDR + 0x56)) 
00319 #define FIO3PINU       (*(reg16_t *)(FIO_BASE_ADDR + 0x76)) 
00320 #define FIO4PINU       (*(reg16_t *)(FIO_BASE_ADDR + 0x96)) 
00321 
00322 #define FIO0SET0       (*(reg8_t *)(FIO_BASE_ADDR + 0x18)) 
00323 #define FIO1SET0       (*(reg8_t *)(FIO_BASE_ADDR + 0x38)) 
00324 #define FIO2SET0       (*(reg8_t *)(FIO_BASE_ADDR + 0x58)) 
00325 #define FIO3SET0       (*(reg8_t *)(FIO_BASE_ADDR + 0x78)) 
00326 #define FIO4SET0       (*(reg8_t *)(FIO_BASE_ADDR + 0x98)) 
00327 
00328 #define FIO0SET1       (*(reg8_t *)(FIO_BASE_ADDR + 0x19)) 
00329 #define FIO1SET1       (*(reg8_t *)(FIO_BASE_ADDR + 0x29)) 
00330 #define FIO2SET1       (*(reg8_t *)(FIO_BASE_ADDR + 0x59)) 
00331 #define FIO3SET1       (*(reg8_t *)(FIO_BASE_ADDR + 0x79)) 
00332 #define FIO4SET1       (*(reg8_t *)(FIO_BASE_ADDR + 0x99)) 
00333 
00334 #define FIO0SET2       (*(reg8_t *)(FIO_BASE_ADDR + 0x1A)) 
00335 #define FIO1SET2       (*(reg8_t *)(FIO_BASE_ADDR + 0x3A)) 
00336 #define FIO2SET2       (*(reg8_t *)(FIO_BASE_ADDR + 0x5A)) 
00337 #define FIO3SET2       (*(reg8_t *)(FIO_BASE_ADDR + 0x7A)) 
00338 #define FIO4SET2       (*(reg8_t *)(FIO_BASE_ADDR + 0x9A)) 
00339 
00340 #define FIO0SET3       (*(reg8_t *)(FIO_BASE_ADDR + 0x1B)) 
00341 #define FIO1SET3       (*(reg8_t *)(FIO_BASE_ADDR + 0x3B)) 
00342 #define FIO2SET3       (*(reg8_t *)(FIO_BASE_ADDR + 0x5B)) 
00343 #define FIO3SET3       (*(reg8_t *)(FIO_BASE_ADDR + 0x7B)) 
00344 #define FIO4SET3       (*(reg8_t *)(FIO_BASE_ADDR + 0x9B)) 
00345 
00346 #define FIO0SETL       (*(reg16_t *)(FIO_BASE_ADDR + 0x18)) 
00347 #define FIO1SETL       (*(reg16_t *)(FIO_BASE_ADDR + 0x38)) 
00348 #define FIO2SETL       (*(reg16_t *)(FIO_BASE_ADDR + 0x58)) 
00349 #define FIO3SETL       (*(reg16_t *)(FIO_BASE_ADDR + 0x78)) 
00350 #define FIO4SETL       (*(reg16_t *)(FIO_BASE_ADDR + 0x98)) 
00351 
00352 #define FIO0SETU       (*(reg16_t *)(FIO_BASE_ADDR + 0x1A)) 
00353 #define FIO1SETU       (*(reg16_t *)(FIO_BASE_ADDR + 0x3A)) 
00354 #define FIO2SETU       (*(reg16_t *)(FIO_BASE_ADDR + 0x5A)) 
00355 #define FIO3SETU       (*(reg16_t *)(FIO_BASE_ADDR + 0x7A)) 
00356 #define FIO4SETU       (*(reg16_t *)(FIO_BASE_ADDR + 0x9A)) 
00357 
00358 #define FIO0CLR0       (*(reg8_t *)(FIO_BASE_ADDR + 0x1C)) 
00359 #define FIO1CLR0       (*(reg8_t *)(FIO_BASE_ADDR + 0x3C)) 
00360 #define FIO2CLR0       (*(reg8_t *)(FIO_BASE_ADDR + 0x5C)) 
00361 #define FIO3CLR0       (*(reg8_t *)(FIO_BASE_ADDR + 0x7C)) 
00362 #define FIO4CLR0       (*(reg8_t *)(FIO_BASE_ADDR + 0x9C)) 
00363 
00364 #define FIO0CLR1       (*(reg8_t *)(FIO_BASE_ADDR + 0x1D)) 
00365 #define FIO1CLR1       (*(reg8_t *)(FIO_BASE_ADDR + 0x2D)) 
00366 #define FIO2CLR1       (*(reg8_t *)(FIO_BASE_ADDR + 0x5D)) 
00367 #define FIO3CLR1       (*(reg8_t *)(FIO_BASE_ADDR + 0x7D)) 
00368 #define FIO4CLR1       (*(reg8_t *)(FIO_BASE_ADDR + 0x9D)) 
00369 
00370 #define FIO0CLR2       (*(reg8_t *)(FIO_BASE_ADDR + 0x1E)) 
00371 #define FIO1CLR2       (*(reg8_t *)(FIO_BASE_ADDR + 0x3E)) 
00372 #define FIO2CLR2       (*(reg8_t *)(FIO_BASE_ADDR + 0x5E)) 
00373 #define FIO3CLR2       (*(reg8_t *)(FIO_BASE_ADDR + 0x7E)) 
00374 #define FIO4CLR2       (*(reg8_t *)(FIO_BASE_ADDR + 0x9E)) 
00375 
00376 #define FIO0CLR3       (*(reg8_t *)(FIO_BASE_ADDR + 0x1F)) 
00377 #define FIO1CLR3       (*(reg8_t *)(FIO_BASE_ADDR + 0x3F)) 
00378 #define FIO2CLR3       (*(reg8_t *)(FIO_BASE_ADDR + 0x5F)) 
00379 #define FIO3CLR3       (*(reg8_t *)(FIO_BASE_ADDR + 0x7F)) 
00380 #define FIO4CLR3       (*(reg8_t *)(FIO_BASE_ADDR + 0x9F)) 
00381 
00382 #define FIO0CLRL       (*(reg16_t *)(FIO_BASE_ADDR + 0x1C)) 
00383 #define FIO1CLRL       (*(reg16_t *)(FIO_BASE_ADDR + 0x3C)) 
00384 #define FIO2CLRL       (*(reg16_t *)(FIO_BASE_ADDR + 0x5C)) 
00385 #define FIO3CLRL       (*(reg16_t *)(FIO_BASE_ADDR + 0x7C)) 
00386 #define FIO4CLRL       (*(reg16_t *)(FIO_BASE_ADDR + 0x9C)) 
00387 
00388 #define FIO0CLRU       (*(reg16_t *)(FIO_BASE_ADDR + 0x1E)) 
00389 #define FIO1CLRU       (*(reg16_t *)(FIO_BASE_ADDR + 0x3E)) 
00390 #define FIO2CLRU       (*(reg16_t *)(FIO_BASE_ADDR + 0x5E)) 
00391 #define FIO3CLRU       (*(reg16_t *)(FIO_BASE_ADDR + 0x7E)) 
00392 #define FIO4CLRU       (*(reg16_t *)(FIO_BASE_ADDR + 0x9E)) 
00393 
00394 
00395 /* System Control Block(SCB) modules include Memory Accelerator Module,
00396 Phase Locked Loop, VPB divider, Power Control, External Interrupt, 
00397 Reset, and Code Security/Debugging */
00398 #define SCB_BASE_ADDR   0xE01FC000
00399 
00400 /* Memory Accelerator Module (MAM) */
00401 #define MAMCR          (*(reg32_t *)(SCB_BASE_ADDR + 0x000))
00402 #define MAMTIM         (*(reg32_t *)(SCB_BASE_ADDR + 0x004))
00403 #define MEMMAP         (*(reg32_t *)(SCB_BASE_ADDR + 0x040))
00404 
00405 /* Phase Locked Loop (PLL) */
00406 #define PLLCON         (*(reg32_t *)(SCB_BASE_ADDR + 0x080))
00407 #define PLLCFG         (*(reg32_t *)(SCB_BASE_ADDR + 0x084))
00408 #define PLLSTAT        (*(reg32_t *)(SCB_BASE_ADDR + 0x088))
00409 #define PLLFEED        (*(reg32_t *)(SCB_BASE_ADDR + 0x08C))
00410 
00411 /* Power Control */
00412 #define PCON           (*(reg32_t *)(SCB_BASE_ADDR + 0x0C0))
00413 #define PCONP          (*(reg32_t *)(SCB_BASE_ADDR + 0x0C4))
00414 
00415 /* Clock Divider */
00416 // #define APBDIV         (*(reg32_t *)(SCB_BASE_ADDR + 0x100))
00417 #define CCLKCFG        (*(reg32_t *)(SCB_BASE_ADDR + 0x104))
00418 #define USBCLKCFG      (*(reg32_t *)(SCB_BASE_ADDR + 0x108))
00419 #define CLKSRCSEL      (*(reg32_t *)(SCB_BASE_ADDR + 0x10C))
00420 #define PCLKSEL0       (*(reg32_t *)(SCB_BASE_ADDR + 0x1A8))
00421 #define PCLKSEL1       (*(reg32_t *)(SCB_BASE_ADDR + 0x1AC))
00422     
00423 /* External Interrupts */
00424 #define EXTINT         (*(reg32_t *)(SCB_BASE_ADDR + 0x140))
00425 #define INTWAKE        (*(reg32_t *)(SCB_BASE_ADDR + 0x144))
00426 #define EXTMODE        (*(reg32_t *)(SCB_BASE_ADDR + 0x148))
00427 #define EXTPOLAR       (*(reg32_t *)(SCB_BASE_ADDR + 0x14C))
00428 
00429 /* Reset, reset source identification */
00430 #define RSIR           (*(reg32_t *)(SCB_BASE_ADDR + 0x180))
00431 
00432 /* RSID, code security protection */
00433 #define CSPR           (*(reg32_t *)(SCB_BASE_ADDR + 0x184))
00434 
00435 /* AHB configuration */
00436 #define AHBCFG1        (*(reg32_t *)(SCB_BASE_ADDR + 0x188))
00437 #define AHBCFG2        (*(reg32_t *)(SCB_BASE_ADDR + 0x18C))
00438 
00439 /* System Controls and Status */
00440 #define SCS            (*(reg32_t *)(SCB_BASE_ADDR + 0x1A0))    
00441 
00442 /* MPMC(EMC) registers, note: all the external memory controller(EMC) registers 
00443 are for LPC24xx only. */
00444 #define STATIC_MEM0_BASE        0x80000000
00445 #define STATIC_MEM1_BASE        0x81000000
00446 #define STATIC_MEM2_BASE        0x82000000
00447 #define STATIC_MEM3_BASE        0x83000000
00448 
00449 #define DYNAMIC_MEM0_BASE       0xA0000000
00450 #define DYNAMIC_MEM1_BASE       0xB0000000
00451 #define DYNAMIC_MEM2_BASE       0xC0000000
00452 #define DYNAMIC_MEM3_BASE       0xD0000000
00453 
00454 /* External Memory Controller (EMC) */
00455 #define EMC_BASE_ADDR       0xFFE08000
00456 #define EMC_CTRL       (*(reg32_t *)(EMC_BASE_ADDR + 0x000))
00457 #define EMC_STAT       (*(reg32_t *)(EMC_BASE_ADDR + 0x004))
00458 #define EMC_CONFIG     (*(reg32_t *)(EMC_BASE_ADDR + 0x008))
00459 
00460 /* Dynamic RAM access registers */
00461 #define EMC_DYN_CTRL     (*(reg32_t *)(EMC_BASE_ADDR + 0x020))
00462 #define EMC_DYN_RFSH     (*(reg32_t *)(EMC_BASE_ADDR + 0x024))
00463 #define EMC_DYN_RD_CFG   (*(reg32_t *)(EMC_BASE_ADDR + 0x028))
00464 #define EMC_DYN_RP       (*(reg32_t *)(EMC_BASE_ADDR + 0x030))
00465 #define EMC_DYN_RAS      (*(reg32_t *)(EMC_BASE_ADDR + 0x034))
00466 #define EMC_DYN_SREX     (*(reg32_t *)(EMC_BASE_ADDR + 0x038))
00467 #define EMC_DYN_APR      (*(reg32_t *)(EMC_BASE_ADDR + 0x03C))
00468 #define EMC_DYN_DAL      (*(reg32_t *)(EMC_BASE_ADDR + 0x040))
00469 #define EMC_DYN_WR       (*(reg32_t *)(EMC_BASE_ADDR + 0x044))
00470 #define EMC_DYN_RC       (*(reg32_t *)(EMC_BASE_ADDR + 0x048))
00471 #define EMC_DYN_RFC      (*(reg32_t *)(EMC_BASE_ADDR + 0x04C))
00472 #define EMC_DYN_XSR      (*(reg32_t *)(EMC_BASE_ADDR + 0x050))
00473 #define EMC_DYN_RRD      (*(reg32_t *)(EMC_BASE_ADDR + 0x054))
00474 #define EMC_DYN_MRD      (*(reg32_t *)(EMC_BASE_ADDR + 0x058))
00475 
00476 #define EMC_DYN_CFG0     (*(reg32_t *)(EMC_BASE_ADDR + 0x100))
00477 #define EMC_DYN_RASCAS0  (*(reg32_t *)(EMC_BASE_ADDR + 0x104))
00478 #define EMC_DYN_CFG1     (*(reg32_t *)(EMC_BASE_ADDR + 0x140))
00479 #define EMC_DYN_RASCAS1  (*(reg32_t *)(EMC_BASE_ADDR + 0x144))
00480 #define EMC_DYN_CFG2     (*(reg32_t *)(EMC_BASE_ADDR + 0x160))
00481 #define EMC_DYN_RASCAS2  (*(reg32_t *)(EMC_BASE_ADDR + 0x164))
00482 #define EMC_DYN_CFG3     (*(reg32_t *)(EMC_BASE_ADDR + 0x180))
00483 #define EMC_DYN_RASCAS3  (*(reg32_t *)(EMC_BASE_ADDR + 0x184))
00484 
00485 /* static RAM access registers */
00486 #define EMC_STA_CFG0      (*(reg32_t *)(EMC_BASE_ADDR + 0x200))
00487 #define EMC_STA_WAITWEN0  (*(reg32_t *)(EMC_BASE_ADDR + 0x204))
00488 #define EMC_STA_WAITOEN0  (*(reg32_t *)(EMC_BASE_ADDR + 0x208))
00489 #define EMC_STA_WAITRD0   (*(reg32_t *)(EMC_BASE_ADDR + 0x20C))
00490 #define EMC_STA_WAITPAGE0 (*(reg32_t *)(EMC_BASE_ADDR + 0x210))
00491 #define EMC_STA_WAITWR0   (*(reg32_t *)(EMC_BASE_ADDR + 0x214))
00492 #define EMC_STA_WAITTURN0 (*(reg32_t *)(EMC_BASE_ADDR + 0x218))
00493 
00494 #define EMC_STA_CFG1      (*(reg32_t *)(EMC_BASE_ADDR + 0x220))
00495 #define EMC_STA_WAITWEN1  (*(reg32_t *)(EMC_BASE_ADDR + 0x224))
00496 #define EMC_STA_WAITOEN1  (*(reg32_t *)(EMC_BASE_ADDR + 0x228))
00497 #define EMC_STA_WAITRD1   (*(reg32_t *)(EMC_BASE_ADDR + 0x22C))
00498 #define EMC_STA_WAITPAGE1 (*(reg32_t *)(EMC_BASE_ADDR + 0x230))
00499 #define EMC_STA_WAITWR1   (*(reg32_t *)(EMC_BASE_ADDR + 0x234))
00500 #define EMC_STA_WAITTURN1 (*(reg32_t *)(EMC_BASE_ADDR + 0x238))
00501 
00502 #define EMC_STA_CFG2      (*(reg32_t *)(EMC_BASE_ADDR + 0x240))
00503 #define EMC_STA_WAITWEN2  (*(reg32_t *)(EMC_BASE_ADDR + 0x244))
00504 #define EMC_STA_WAITOEN2  (*(reg32_t *)(EMC_BASE_ADDR + 0x248))
00505 #define EMC_STA_WAITRD2   (*(reg32_t *)(EMC_BASE_ADDR + 0x24C))
00506 #define EMC_STA_WAITPAGE2 (*(reg32_t *)(EMC_BASE_ADDR + 0x250))
00507 #define EMC_STA_WAITWR2   (*(reg32_t *)(EMC_BASE_ADDR + 0x254))
00508 #define EMC_STA_WAITTURN2 (*(reg32_t *)(EMC_BASE_ADDR + 0x258))
00509 
00510 #define EMC_STA_CFG3      (*(reg32_t *)(EMC_BASE_ADDR + 0x260))
00511 #define EMC_STA_WAITWEN3  (*(reg32_t *)(EMC_BASE_ADDR + 0x264))
00512 #define EMC_STA_WAITOEN3  (*(reg32_t *)(EMC_BASE_ADDR + 0x268))
00513 #define EMC_STA_WAITRD3   (*(reg32_t *)(EMC_BASE_ADDR + 0x26C))
00514 #define EMC_STA_WAITPAGE3 (*(reg32_t *)(EMC_BASE_ADDR + 0x270))
00515 #define EMC_STA_WAITWR3   (*(reg32_t *)(EMC_BASE_ADDR + 0x274))
00516 #define EMC_STA_WAITTURN3 (*(reg32_t *)(EMC_BASE_ADDR + 0x278))
00517 
00518 #define EMC_STA_EXT_WAIT  (*(reg32_t *)(EMC_BASE_ADDR + 0x880))
00519 
00520     
00521 /* Timer 0 */
00522 #define TMR0_BASE_ADDR      0xE0004000
00523 #define T0IR           (*(reg32_t *)(TMR0_BASE_ADDR + 0x00))
00524 #define T0TCR          (*(reg32_t *)(TMR0_BASE_ADDR + 0x04))
00525 #define T0TC           (*(reg32_t *)(TMR0_BASE_ADDR + 0x08))
00526 #define T0PR           (*(reg32_t *)(TMR0_BASE_ADDR + 0x0C))
00527 #define T0PC           (*(reg32_t *)(TMR0_BASE_ADDR + 0x10))
00528 #define T0MCR          (*(reg32_t *)(TMR0_BASE_ADDR + 0x14))
00529 #define T0MR0          (*(reg32_t *)(TMR0_BASE_ADDR + 0x18))
00530 #define T0MR1          (*(reg32_t *)(TMR0_BASE_ADDR + 0x1C))
00531 #define T0MR2          (*(reg32_t *)(TMR0_BASE_ADDR + 0x20))
00532 #define T0MR3          (*(reg32_t *)(TMR0_BASE_ADDR + 0x24))
00533 #define T0CCR          (*(reg32_t *)(TMR0_BASE_ADDR + 0x28))
00534 #define T0CR0          (*(reg32_t *)(TMR0_BASE_ADDR + 0x2C))
00535 #define T0CR1          (*(reg32_t *)(TMR0_BASE_ADDR + 0x30))
00536 #define T0CR2          (*(reg32_t *)(TMR0_BASE_ADDR + 0x34))
00537 #define T0CR3          (*(reg32_t *)(TMR0_BASE_ADDR + 0x38))
00538 #define T0EMR          (*(reg32_t *)(TMR0_BASE_ADDR + 0x3C))
00539 #define T0CTCR         (*(reg32_t *)(TMR0_BASE_ADDR + 0x70))
00540 
00541 /* Timer 1 */
00542 #define TMR1_BASE_ADDR      0xE0008000
00543 #define T1IR           (*(reg32_t *)(TMR1_BASE_ADDR + 0x00))
00544 #define T1TCR          (*(reg32_t *)(TMR1_BASE_ADDR + 0x04))
00545 #define T1TC           (*(reg32_t *)(TMR1_BASE_ADDR + 0x08))
00546 #define T1PR           (*(reg32_t *)(TMR1_BASE_ADDR + 0x0C))
00547 #define T1PC           (*(reg32_t *)(TMR1_BASE_ADDR + 0x10))
00548 #define T1MCR          (*(reg32_t *)(TMR1_BASE_ADDR + 0x14))
00549 #define T1MR0          (*(reg32_t *)(TMR1_BASE_ADDR + 0x18))
00550 #define T1MR1          (*(reg32_t *)(TMR1_BASE_ADDR + 0x1C))
00551 #define T1MR2          (*(reg32_t *)(TMR1_BASE_ADDR + 0x20))
00552 #define T1MR3          (*(reg32_t *)(TMR1_BASE_ADDR + 0x24))
00553 #define T1CCR          (*(reg32_t *)(TMR1_BASE_ADDR + 0x28))
00554 #define T1CR0          (*(reg32_t *)(TMR1_BASE_ADDR + 0x2C))
00555 #define T1CR1          (*(reg32_t *)(TMR1_BASE_ADDR + 0x30))
00556 #define T1CR2          (*(reg32_t *)(TMR1_BASE_ADDR + 0x34))
00557 #define T1CR3          (*(reg32_t *)(TMR1_BASE_ADDR + 0x38))
00558 #define T1EMR          (*(reg32_t *)(TMR1_BASE_ADDR + 0x3C))
00559 #define T1CTCR         (*(reg32_t *)(TMR1_BASE_ADDR + 0x70))
00560 
00561 /* Timer 2 */
00562 #define TMR2_BASE_ADDR      0xE0070000
00563 #define T2IR           (*(reg32_t *)(TMR2_BASE_ADDR + 0x00))
00564 #define T2TCR          (*(reg32_t *)(TMR2_BASE_ADDR + 0x04))
00565 #define T2TC           (*(reg32_t *)(TMR2_BASE_ADDR + 0x08))
00566 #define T2PR           (*(reg32_t *)(TMR2_BASE_ADDR + 0x0C))
00567 #define T2PC           (*(reg32_t *)(TMR2_BASE_ADDR + 0x10))
00568 #define T2MCR          (*(reg32_t *)(TMR2_BASE_ADDR + 0x14))
00569 #define T2MR0          (*(reg32_t *)(TMR2_BASE_ADDR + 0x18))
00570 #define T2MR1          (*(reg32_t *)(TMR2_BASE_ADDR + 0x1C))
00571 #define T2MR2          (*(reg32_t *)(TMR2_BASE_ADDR + 0x20))
00572 #define T2MR3          (*(reg32_t *)(TMR2_BASE_ADDR + 0x24))
00573 #define T2CCR          (*(reg32_t *)(TMR2_BASE_ADDR + 0x28))
00574 #define T2CR0          (*(reg32_t *)(TMR2_BASE_ADDR + 0x2C))
00575 #define T2CR1          (*(reg32_t *)(TMR2_BASE_ADDR + 0x30))
00576 #define T2CR2          (*(reg32_t *)(TMR2_BASE_ADDR + 0x34))
00577 #define T2CR3          (*(reg32_t *)(TMR2_BASE_ADDR + 0x38))
00578 #define T2EMR          (*(reg32_t *)(TMR2_BASE_ADDR + 0x3C))
00579 #define T2CTCR         (*(reg32_t *)(TMR2_BASE_ADDR + 0x70))
00580 
00581 /* Timer 3 */
00582 #define TMR3_BASE_ADDR      0xE0074000
00583 #define T3IR           (*(reg32_t *)(TMR3_BASE_ADDR + 0x00))
00584 #define T3TCR          (*(reg32_t *)(TMR3_BASE_ADDR + 0x04))
00585 #define T3TC           (*(reg32_t *)(TMR3_BASE_ADDR + 0x08))
00586 #define T3PR           (*(reg32_t *)(TMR3_BASE_ADDR + 0x0C))
00587 #define T3PC           (*(reg32_t *)(TMR3_BASE_ADDR + 0x10))
00588 #define T3MCR          (*(reg32_t *)(TMR3_BASE_ADDR + 0x14))
00589 #define T3MR0          (*(reg32_t *)(TMR3_BASE_ADDR + 0x18))
00590 #define T3MR1          (*(reg32_t *)(TMR3_BASE_ADDR + 0x1C))
00591 #define T3MR2          (*(reg32_t *)(TMR3_BASE_ADDR + 0x20))
00592 #define T3MR3          (*(reg32_t *)(TMR3_BASE_ADDR + 0x24))
00593 #define T3CCR          (*(reg32_t *)(TMR3_BASE_ADDR + 0x28))
00594 #define T3CR0          (*(reg32_t *)(TMR3_BASE_ADDR + 0x2C))
00595 #define T3CR1          (*(reg32_t *)(TMR3_BASE_ADDR + 0x30))
00596 #define T3CR2          (*(reg32_t *)(TMR3_BASE_ADDR + 0x34))
00597 #define T3CR3          (*(reg32_t *)(TMR3_BASE_ADDR + 0x38))
00598 #define T3EMR          (*(reg32_t *)(TMR3_BASE_ADDR + 0x3C))
00599 #define T3CTCR         (*(reg32_t *)(TMR3_BASE_ADDR + 0x70))
00600 
00601 
00602 /* Pulse Width Modulator (PWM) */
00603 #define PWM0_BASE_ADDR      0xE0014000
00604 #define PWM0IR          (*(reg32_t *)(PWM0_BASE_ADDR + 0x00))
00605 #define PWM0TCR         (*(reg32_t *)(PWM0_BASE_ADDR + 0x04))
00606 #define PWM0TC          (*(reg32_t *)(PWM0_BASE_ADDR + 0x08))
00607 #define PWM0PR          (*(reg32_t *)(PWM0_BASE_ADDR + 0x0C))
00608 #define PWM0PC          (*(reg32_t *)(PWM0_BASE_ADDR + 0x10))
00609 #define PWM0MCR         (*(reg32_t *)(PWM0_BASE_ADDR + 0x14))
00610 #define PWM0MR0         (*(reg32_t *)(PWM0_BASE_ADDR + 0x18))
00611 #define PWM0MR1         (*(reg32_t *)(PWM0_BASE_ADDR + 0x1C))
00612 #define PWM0MR2         (*(reg32_t *)(PWM0_BASE_ADDR + 0x20))
00613 #define PWM0MR3         (*(reg32_t *)(PWM0_BASE_ADDR + 0x24))
00614 #define PWM0CCR         (*(reg32_t *)(PWM0_BASE_ADDR + 0x28))
00615 #define PWM0CR0         (*(reg32_t *)(PWM0_BASE_ADDR + 0x2C))
00616 #define PWM0CR1         (*(reg32_t *)(PWM0_BASE_ADDR + 0x30))
00617 #define PWM0CR2         (*(reg32_t *)(PWM0_BASE_ADDR + 0x34))
00618 #define PWM0CR3         (*(reg32_t *)(PWM0_BASE_ADDR + 0x38))
00619 #define PWM0EMR         (*(reg32_t *)(PWM0_BASE_ADDR + 0x3C))
00620 #define PWM0MR4         (*(reg32_t *)(PWM0_BASE_ADDR + 0x40))
00621 #define PWM0MR5         (*(reg32_t *)(PWM0_BASE_ADDR + 0x44))
00622 #define PWM0MR6         (*(reg32_t *)(PWM0_BASE_ADDR + 0x48))
00623 #define PWM0PCR         (*(reg32_t *)(PWM0_BASE_ADDR + 0x4C))
00624 #define PWM0LER         (*(reg32_t *)(PWM0_BASE_ADDR + 0x50))
00625 #define PWM0CTCR        (*(reg32_t *)(PWM0_BASE_ADDR + 0x70))
00626 
00627 #define PWM1_BASE_ADDR      0xE0018000
00628 #define PWM1IR          (*(reg32_t *)(PWM1_BASE_ADDR + 0x00))
00629 #define PWM1TCR         (*(reg32_t *)(PWM1_BASE_ADDR + 0x04))
00630 #define PWM1TC          (*(reg32_t *)(PWM1_BASE_ADDR + 0x08))
00631 #define PWM1PR          (*(reg32_t *)(PWM1_BASE_ADDR + 0x0C))
00632 #define PWM1PC          (*(reg32_t *)(PWM1_BASE_ADDR + 0x10))
00633 #define PWM1MCR         (*(reg32_t *)(PWM1_BASE_ADDR + 0x14))
00634 #define PWM1MR0         (*(reg32_t *)(PWM1_BASE_ADDR + 0x18))
00635 #define PWM1MR1         (*(reg32_t *)(PWM1_BASE_ADDR + 0x1C))
00636 #define PWM1MR2         (*(reg32_t *)(PWM1_BASE_ADDR + 0x20))
00637 #define PWM1MR3         (*(reg32_t *)(PWM1_BASE_ADDR + 0x24))
00638 #define PWM1CCR         (*(reg32_t *)(PWM1_BASE_ADDR + 0x28))
00639 #define PWM1CR0         (*(reg32_t *)(PWM1_BASE_ADDR + 0x2C))
00640 #define PWM1CR1         (*(reg32_t *)(PWM1_BASE_ADDR + 0x30))
00641 #define PWM1CR2         (*(reg32_t *)(PWM1_BASE_ADDR + 0x34))
00642 #define PWM1CR3         (*(reg32_t *)(PWM1_BASE_ADDR + 0x38))
00643 #define PWM1EMR         (*(reg32_t *)(PWM1_BASE_ADDR + 0x3C))
00644 #define PWM1MR4         (*(reg32_t *)(PWM1_BASE_ADDR + 0x40))
00645 #define PWM1MR5         (*(reg32_t *)(PWM1_BASE_ADDR + 0x44))
00646 #define PWM1MR6         (*(reg32_t *)(PWM1_BASE_ADDR + 0x48))
00647 #define PWM1PCR         (*(reg32_t *)(PWM1_BASE_ADDR + 0x4C))
00648 #define PWM1LER         (*(reg32_t *)(PWM1_BASE_ADDR + 0x50))
00649 #define PWM1CTCR        (*(reg32_t *)(PWM1_BASE_ADDR + 0x70))
00650 
00651 
00652 /* Universal Asynchronous Receiver Transmitter 0 (UART0) */
00653 #define UART0_BASE_ADDR     0xE000C000
00654 #define U0RBR          (*(reg32_t *)(UART0_BASE_ADDR + 0x00))
00655 #define U0THR          (*(reg32_t *)(UART0_BASE_ADDR + 0x00))
00656 #define U0DLL          (*(reg32_t *)(UART0_BASE_ADDR + 0x00))
00657 #define U0DLM          (*(reg32_t *)(UART0_BASE_ADDR + 0x04))
00658 #define U0IER          (*(reg32_t *)(UART0_BASE_ADDR + 0x04))
00659 #define U0IIR          (*(reg32_t *)(UART0_BASE_ADDR + 0x08))
00660 #define U0FCR          (*(reg32_t *)(UART0_BASE_ADDR + 0x08))
00661 #define U0LCR          (*(reg32_t *)(UART0_BASE_ADDR + 0x0C))
00662 #define U0LSR          (*(reg32_t *)(UART0_BASE_ADDR + 0x14))
00663 #define U0SCR          (*(reg32_t *)(UART0_BASE_ADDR + 0x1C))
00664 #define U0ACR          (*(reg32_t *)(UART0_BASE_ADDR + 0x20))
00665 #define U0ICR          (*(reg32_t *)(UART0_BASE_ADDR + 0x24))
00666 #define U0FDR          (*(reg32_t *)(UART0_BASE_ADDR + 0x28))
00667 #define U0TER          (*(reg32_t *)(UART0_BASE_ADDR + 0x30))
00668 
00669 /* Universal Asynchronous Receiver Transmitter 1 (UART1) */
00670 #define UART1_BASE_ADDR     0xE0010000
00671 #define U1RBR          (*(reg32_t *)(UART1_BASE_ADDR + 0x00))
00672 #define U1THR          (*(reg32_t *)(UART1_BASE_ADDR + 0x00))
00673 #define U1DLL          (*(reg32_t *)(UART1_BASE_ADDR + 0x00))
00674 #define U1DLM          (*(reg32_t *)(UART1_BASE_ADDR + 0x04))
00675 #define U1IER          (*(reg32_t *)(UART1_BASE_ADDR + 0x04))
00676 #define U1IIR          (*(reg32_t *)(UART1_BASE_ADDR + 0x08))
00677 #define U1FCR          (*(reg32_t *)(UART1_BASE_ADDR + 0x08))
00678 #define U1LCR          (*(reg32_t *)(UART1_BASE_ADDR + 0x0C))
00679 #define U1MCR          (*(reg32_t *)(UART1_BASE_ADDR + 0x10))
00680 #define U1LSR          (*(reg32_t *)(UART1_BASE_ADDR + 0x14))
00681 #define U1MSR          (*(reg32_t *)(UART1_BASE_ADDR + 0x18))
00682 #define U1SCR          (*(reg32_t *)(UART1_BASE_ADDR + 0x1C))
00683 #define U1ACR          (*(reg32_t *)(UART1_BASE_ADDR + 0x20))
00684 #define U1FDR          (*(reg32_t *)(UART1_BASE_ADDR + 0x28))
00685 #define U1TER          (*(reg32_t *)(UART1_BASE_ADDR + 0x30))
00686 
00687 /* Universal Asynchronous Receiver Transmitter 2 (UART2) */
00688 #define UART2_BASE_ADDR     0xE0078000
00689 #define U2RBR          (*(reg32_t *)(UART2_BASE_ADDR + 0x00))
00690 #define U2THR          (*(reg32_t *)(UART2_BASE_ADDR + 0x00))
00691 #define U2DLL          (*(reg32_t *)(UART2_BASE_ADDR + 0x00))
00692 #define U2DLM          (*(reg32_t *)(UART2_BASE_ADDR + 0x04))
00693 #define U2IER          (*(reg32_t *)(UART2_BASE_ADDR + 0x04))
00694 #define U2IIR          (*(reg32_t *)(UART2_BASE_ADDR + 0x08))
00695 #define U2FCR          (*(reg32_t *)(UART2_BASE_ADDR + 0x08))
00696 #define U2LCR          (*(reg32_t *)(UART2_BASE_ADDR + 0x0C))
00697 #define U2LSR          (*(reg32_t *)(UART2_BASE_ADDR + 0x14))
00698 #define U2SCR          (*(reg32_t *)(UART2_BASE_ADDR + 0x1C))
00699 #define U2ACR          (*(reg32_t *)(UART2_BASE_ADDR + 0x20))
00700 #define U2ICR          (*(reg32_t *)(UART2_BASE_ADDR + 0x24))
00701 #define U2FDR          (*(reg32_t *)(UART2_BASE_ADDR + 0x28))
00702 #define U2TER          (*(reg32_t *)(UART2_BASE_ADDR + 0x30))
00703 
00704 /* Universal Asynchronous Receiver Transmitter 3 (UART3) */
00705 #define UART3_BASE_ADDR     0xE007C000
00706 #define U3RBR          (*(reg32_t *)(UART3_BASE_ADDR + 0x00))
00707 #define U3THR          (*(reg32_t *)(UART3_BASE_ADDR + 0x00))
00708 #define U3DLL          (*(reg32_t *)(UART3_BASE_ADDR + 0x00))
00709 #define U3DLM          (*(reg32_t *)(UART3_BASE_ADDR + 0x04))
00710 #define U3IER          (*(reg32_t *)(UART3_BASE_ADDR + 0x04))
00711 #define U3IIR          (*(reg32_t *)(UART3_BASE_ADDR + 0x08))
00712 #define U3FCR          (*(reg32_t *)(UART3_BASE_ADDR + 0x08))
00713 #define U3LCR          (*(reg32_t *)(UART3_BASE_ADDR + 0x0C))
00714 #define U3LSR          (*(reg32_t *)(UART3_BASE_ADDR + 0x14))
00715 #define U3SCR          (*(reg32_t *)(UART3_BASE_ADDR + 0x1C))
00716 #define U3ACR          (*(reg32_t *)(UART3_BASE_ADDR + 0x20))
00717 #define U3ICR          (*(reg32_t *)(UART3_BASE_ADDR + 0x24))
00718 #define U3FDR          (*(reg32_t *)(UART3_BASE_ADDR + 0x28))
00719 #define U3TER          (*(reg32_t *)(UART3_BASE_ADDR + 0x30))
00720 
00721 /* I2C Interface 0 */
00722 #define I2C0_BASE_ADDR      0xE001C000
00723 #define I20CONSET      (*(reg32_t *)(I2C0_BASE_ADDR + 0x00))
00724 #define I20STAT        (*(reg32_t *)(I2C0_BASE_ADDR + 0x04))
00725 #define I20DAT         (*(reg32_t *)(I2C0_BASE_ADDR + 0x08))
00726 #define I20ADR         (*(reg32_t *)(I2C0_BASE_ADDR + 0x0C))
00727 #define I20SCLH        (*(reg32_t *)(I2C0_BASE_ADDR + 0x10))
00728 #define I20SCLL        (*(reg32_t *)(I2C0_BASE_ADDR + 0x14))
00729 #define I20CONCLR      (*(reg32_t *)(I2C0_BASE_ADDR + 0x18))
00730 
00731 /* I2C Interface 1 */
00732 #define I2C1_BASE_ADDR      0xE005C000
00733 #define I21CONSET      (*(reg32_t *)(I2C1_BASE_ADDR + 0x00))
00734 #define I21STAT        (*(reg32_t *)(I2C1_BASE_ADDR + 0x04))
00735 #define I21DAT         (*(reg32_t *)(I2C1_BASE_ADDR + 0x08))
00736 #define I21ADR         (*(reg32_t *)(I2C1_BASE_ADDR + 0x0C))
00737 #define I21SCLH        (*(reg32_t *)(I2C1_BASE_ADDR + 0x10))
00738 #define I21SCLL        (*(reg32_t *)(I2C1_BASE_ADDR + 0x14))
00739 #define I21CONCLR      (*(reg32_t *)(I2C1_BASE_ADDR + 0x18))
00740 
00741 /* I2C Interface 2 */
00742 #define I2C2_BASE_ADDR      0xE0080000
00743 #define I22CONSET      (*(reg32_t *)(I2C2_BASE_ADDR + 0x00))
00744 #define I22STAT        (*(reg32_t *)(I2C2_BASE_ADDR + 0x04))
00745 #define I22DAT         (*(reg32_t *)(I2C2_BASE_ADDR + 0x08))
00746 #define I22ADR         (*(reg32_t *)(I2C2_BASE_ADDR + 0x0C))
00747 #define I22SCLH        (*(reg32_t *)(I2C2_BASE_ADDR + 0x10))
00748 #define I22SCLL        (*(reg32_t *)(I2C2_BASE_ADDR + 0x14))
00749 #define I22CONCLR      (*(reg32_t *)(I2C2_BASE_ADDR + 0x18))
00750 
00751 /* SPI0 (Serial Peripheral Interface 0) */
00752 #define SPI0_BASE_ADDR      0xE0020000
00753 #define S0SPCR         (*(reg32_t *)(SPI0_BASE_ADDR + 0x00))
00754 #define S0SPSR         (*(reg32_t *)(SPI0_BASE_ADDR + 0x04))
00755 #define S0SPDR         (*(reg32_t *)(SPI0_BASE_ADDR + 0x08))
00756 #define S0SPCCR        (*(reg32_t *)(SPI0_BASE_ADDR + 0x0C))
00757 #define S0SPINT        (*(reg32_t *)(SPI0_BASE_ADDR + 0x1C))
00758 
00759 /* SSP0 Controller */
00760 #define SSP0_BASE_ADDR      0xE0068000
00761 #define SSP0CR0        (*(reg32_t *)(SSP0_BASE_ADDR + 0x00))
00762 #define SSP0CR1        (*(reg32_t *)(SSP0_BASE_ADDR + 0x04))
00763 #define SSP0DR         (*(reg32_t *)(SSP0_BASE_ADDR + 0x08))
00764 #define SSP0SR         (*(reg32_t *)(SSP0_BASE_ADDR + 0x0C))
00765 #define SSP0CPSR       (*(reg32_t *)(SSP0_BASE_ADDR + 0x10))
00766 #define SSP0IMSC       (*(reg32_t *)(SSP0_BASE_ADDR + 0x14))
00767 #define SSP0RIS        (*(reg32_t *)(SSP0_BASE_ADDR + 0x18))
00768 #define SSP0MIS        (*(reg32_t *)(SSP0_BASE_ADDR + 0x1C))
00769 #define SSP0ICR        (*(reg32_t *)(SSP0_BASE_ADDR + 0x20))
00770 #define SSP0DMACR      (*(reg32_t *)(SSP0_BASE_ADDR + 0x24))
00771 
00772 /* SSP1 Controller */
00773 #define SSP1_BASE_ADDR      0xE0030000
00774 #define SSP1CR0        (*(reg32_t *)(SSP1_BASE_ADDR + 0x00))
00775 #define SSP1CR1        (*(reg32_t *)(SSP1_BASE_ADDR + 0x04))
00776 #define SSP1DR         (*(reg32_t *)(SSP1_BASE_ADDR + 0x08))
00777 #define SSP1SR         (*(reg32_t *)(SSP1_BASE_ADDR + 0x0C))
00778 #define SSP1CPSR       (*(reg32_t *)(SSP1_BASE_ADDR + 0x10))
00779 #define SSP1IMSC       (*(reg32_t *)(SSP1_BASE_ADDR + 0x14))
00780 #define SSP1RIS        (*(reg32_t *)(SSP1_BASE_ADDR + 0x18))
00781 #define SSP1MIS        (*(reg32_t *)(SSP1_BASE_ADDR + 0x1C))
00782 #define SSP1ICR        (*(reg32_t *)(SSP1_BASE_ADDR + 0x20))
00783 #define SSP1DMACR      (*(reg32_t *)(SSP1_BASE_ADDR + 0x24))
00784 
00785 
00786 /* Real Time Clock */
00787 #define RTC_BASE_ADDR       0xE0024000
00788 #define RTC_ILR         (*(reg32_t *)(RTC_BASE_ADDR + 0x00))
00789 #define RTC_CTC         (*(reg32_t *)(RTC_BASE_ADDR + 0x04))
00790 #define RTC_CCR         (*(reg32_t *)(RTC_BASE_ADDR + 0x08))
00791 #define RTC_CIIR        (*(reg32_t *)(RTC_BASE_ADDR + 0x0C))
00792 #define RTC_AMR         (*(reg32_t *)(RTC_BASE_ADDR + 0x10))
00793 #define RTC_CTIME0      (*(reg32_t *)(RTC_BASE_ADDR + 0x14))
00794 #define RTC_CTIME1      (*(reg32_t *)(RTC_BASE_ADDR + 0x18))
00795 #define RTC_CTIME2      (*(reg32_t *)(RTC_BASE_ADDR + 0x1C))
00796 #define RTC_SEC         (*(reg32_t *)(RTC_BASE_ADDR + 0x20))
00797 #define RTC_MIN         (*(reg32_t *)(RTC_BASE_ADDR + 0x24))
00798 #define RTC_HOUR        (*(reg32_t *)(RTC_BASE_ADDR + 0x28))
00799 #define RTC_DOM         (*(reg32_t *)(RTC_BASE_ADDR + 0x2C))
00800 #define RTC_DOW         (*(reg32_t *)(RTC_BASE_ADDR + 0x30))
00801 #define RTC_DOY         (*(reg32_t *)(RTC_BASE_ADDR + 0x34))
00802 #define RTC_MONTH       (*(reg32_t *)(RTC_BASE_ADDR + 0x38))
00803 #define RTC_YEAR        (*(reg32_t *)(RTC_BASE_ADDR + 0x3C))
00804 #define RTC_CISS        (*(reg32_t *)(RTC_BASE_ADDR + 0x40))
00805 #define RTC_ALSEC       (*(reg32_t *)(RTC_BASE_ADDR + 0x60))
00806 #define RTC_ALMIN       (*(reg32_t *)(RTC_BASE_ADDR + 0x64))
00807 #define RTC_ALHOUR      (*(reg32_t *)(RTC_BASE_ADDR + 0x68))
00808 #define RTC_ALDOM       (*(reg32_t *)(RTC_BASE_ADDR + 0x6C))
00809 #define RTC_ALDOW       (*(reg32_t *)(RTC_BASE_ADDR + 0x70))
00810 #define RTC_ALDOY       (*(reg32_t *)(RTC_BASE_ADDR + 0x74))
00811 #define RTC_ALMON       (*(reg32_t *)(RTC_BASE_ADDR + 0x78))
00812 #define RTC_ALYEAR      (*(reg32_t *)(RTC_BASE_ADDR + 0x7C))
00813 #define RTC_PREINT      (*(reg32_t *)(RTC_BASE_ADDR + 0x80))
00814 #define RTC_PREFRAC     (*(reg32_t *)(RTC_BASE_ADDR + 0x84))
00815 
00816 
00817 /* A/D Converter 0 (AD0) */
00818 #define AD0_BASE_ADDR       0xE0034000
00819 #define AD0CR          (*(reg32_t *)(AD0_BASE_ADDR + 0x00))
00820 #define AD0GDR         (*(reg32_t *)(AD0_BASE_ADDR + 0x04))
00821 #define AD0INTEN       (*(reg32_t *)(AD0_BASE_ADDR + 0x0C))
00822 #define AD0DR0         (*(reg32_t *)(AD0_BASE_ADDR + 0x10))
00823 #define AD0DR1         (*(reg32_t *)(AD0_BASE_ADDR + 0x14))
00824 #define AD0DR2         (*(reg32_t *)(AD0_BASE_ADDR + 0x18))
00825 #define AD0DR3         (*(reg32_t *)(AD0_BASE_ADDR + 0x1C))
00826 #define AD0DR4         (*(reg32_t *)(AD0_BASE_ADDR + 0x20))
00827 #define AD0DR5         (*(reg32_t *)(AD0_BASE_ADDR + 0x24))
00828 #define AD0DR6         (*(reg32_t *)(AD0_BASE_ADDR + 0x28))
00829 #define AD0DR7         (*(reg32_t *)(AD0_BASE_ADDR + 0x2C))
00830 #define AD0STAT        (*(reg32_t *)(AD0_BASE_ADDR + 0x30))
00831 
00832 
00833 /* D/A Converter */
00834 #define DAC_BASE_ADDR       0xE006C000
00835 #define DACR           (*(reg32_t *)(DAC_BASE_ADDR + 0x00))
00836 
00837 
00838 /* Watchdog */
00839 #define WDG_BASE_ADDR       0xE0000000
00840 #define WDMOD          (*(reg32_t *)(WDG_BASE_ADDR + 0x00))
00841 #define WDTC           (*(reg32_t *)(WDG_BASE_ADDR + 0x04))
00842 #define WDFEED         (*(reg32_t *)(WDG_BASE_ADDR + 0x08))
00843 #define WDTV           (*(reg32_t *)(WDG_BASE_ADDR + 0x0C))
00844 #define WDCLKSEL       (*(reg32_t *)(WDG_BASE_ADDR + 0x10))
00845 
00846 /* CAN CONTROLLERS AND ACCEPTANCE FILTER */
00847 #define CAN_ACCEPT_BASE_ADDR        0xE003C000
00848 #define CAN_AFMR        (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x00))     
00849 #define CAN_SFF_SA      (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x04))     
00850 #define CAN_SFF_GRP_SA  (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x08))
00851 #define CAN_EFF_SA      (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x0C))
00852 #define CAN_EFF_GRP_SA  (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x10))     
00853 #define CAN_EOT         (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x14))
00854 #define CAN_LUT_ERR_ADR (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x18))     
00855 #define CAN_LUT_ERR     (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x1C))
00856 
00857 #define CAN_CENTRAL_BASE_ADDR       0xE0040000      
00858 #define CAN_TX_SR   (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x00))    
00859 #define CAN_RX_SR   (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x04))    
00860 #define CAN_MSR     (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x08))
00861 
00862 #define CAN1_BASE_ADDR      0xE0044000
00863 #define CAN1MOD     (*(reg32_t *)(CAN1_BASE_ADDR + 0x00))   
00864 #define CAN1CMR     (*(reg32_t *)(CAN1_BASE_ADDR + 0x04))   
00865 #define CAN1GSR     (*(reg32_t *)(CAN1_BASE_ADDR + 0x08))   
00866 #define CAN1ICR     (*(reg32_t *)(CAN1_BASE_ADDR + 0x0C))   
00867 #define CAN1IER     (*(reg32_t *)(CAN1_BASE_ADDR + 0x10))
00868 #define CAN1BTR     (*(reg32_t *)(CAN1_BASE_ADDR + 0x14))   
00869 #define CAN1EWL     (*(reg32_t *)(CAN1_BASE_ADDR + 0x18))   
00870 #define CAN1SR      (*(reg32_t *)(CAN1_BASE_ADDR + 0x1C))   
00871 #define CAN1RFS     (*(reg32_t *)(CAN1_BASE_ADDR + 0x20))   
00872 #define CAN1RID     (*(reg32_t *)(CAN1_BASE_ADDR + 0x24))
00873 #define CAN1RDA     (*(reg32_t *)(CAN1_BASE_ADDR + 0x28))   
00874 #define CAN1RDB     (*(reg32_t *)(CAN1_BASE_ADDR + 0x2C))
00875     
00876 #define CAN1TFI1    (*(reg32_t *)(CAN1_BASE_ADDR + 0x30))   
00877 #define CAN1TID1    (*(reg32_t *)(CAN1_BASE_ADDR + 0x34))   
00878 #define CAN1TDA1    (*(reg32_t *)(CAN1_BASE_ADDR + 0x38))
00879 #define CAN1TDB1    (*(reg32_t *)(CAN1_BASE_ADDR + 0x3C))   
00880 #define CAN1TFI2    (*(reg32_t *)(CAN1_BASE_ADDR + 0x40))   
00881 #define CAN1TID2    (*(reg32_t *)(CAN1_BASE_ADDR + 0x44))   
00882 #define CAN1TDA2    (*(reg32_t *)(CAN1_BASE_ADDR + 0x48))   
00883 #define CAN1TDB2    (*(reg32_t *)(CAN1_BASE_ADDR + 0x4C))
00884 #define CAN1TFI3    (*(reg32_t *)(CAN1_BASE_ADDR + 0x50))   
00885 #define CAN1TID3    (*(reg32_t *)(CAN1_BASE_ADDR + 0x54))   
00886 #define CAN1TDA3    (*(reg32_t *)(CAN1_BASE_ADDR + 0x58))   
00887 #define CAN1TDB3    (*(reg32_t *)(CAN1_BASE_ADDR + 0x5C))
00888 
00889 #define CAN2_BASE_ADDR      0xE0048000
00890 #define CAN2MOD     (*(reg32_t *)(CAN2_BASE_ADDR + 0x00))   
00891 #define CAN2CMR     (*(reg32_t *)(CAN2_BASE_ADDR + 0x04))   
00892 #define CAN2GSR     (*(reg32_t *)(CAN2_BASE_ADDR + 0x08))   
00893 #define CAN2ICR     (*(reg32_t *)(CAN2_BASE_ADDR + 0x0C))   
00894 #define CAN2IER     (*(reg32_t *)(CAN2_BASE_ADDR + 0x10))
00895 #define CAN2BTR     (*(reg32_t *)(CAN2_BASE_ADDR + 0x14))   
00896 #define CAN2EWL     (*(reg32_t *)(CAN2_BASE_ADDR + 0x18))   
00897 #define CAN2SR      (*(reg32_t *)(CAN2_BASE_ADDR + 0x1C))   
00898 #define CAN2RFS     (*(reg32_t *)(CAN2_BASE_ADDR + 0x20))   
00899 #define CAN2RID     (*(reg32_t *)(CAN2_BASE_ADDR + 0x24))
00900 #define CAN2RDA     (*(reg32_t *)(CAN2_BASE_ADDR + 0x28))   
00901 #define CAN2RDB     (*(reg32_t *)(CAN2_BASE_ADDR + 0x2C))
00902     
00903 #define CAN2TFI1    (*(reg32_t *)(CAN2_BASE_ADDR + 0x30))   
00904 #define CAN2TID1    (*(reg32_t *)(CAN2_BASE_ADDR + 0x34))   
00905 #define CAN2TDA1    (*(reg32_t *)(CAN2_BASE_ADDR + 0x38))
00906 #define CAN2TDB1    (*(reg32_t *)(CAN2_BASE_ADDR + 0x3C))   
00907 #define CAN2TFI2    (*(reg32_t *)(CAN2_BASE_ADDR + 0x40))   
00908 #define CAN2TID2    (*(reg32_t *)(CAN2_BASE_ADDR + 0x44))   
00909 #define CAN2TDA2    (*(reg32_t *)(CAN2_BASE_ADDR + 0x48))   
00910 #define CAN2TDB2    (*(reg32_t *)(CAN2_BASE_ADDR + 0x4C))
00911 #define CAN2TFI3    (*(reg32_t *)(CAN2_BASE_ADDR + 0x50))   
00912 #define CAN2TID3    (*(reg32_t *)(CAN2_BASE_ADDR + 0x54))   
00913 #define CAN2TDA3    (*(reg32_t *)(CAN2_BASE_ADDR + 0x58))   
00914 #define CAN2TDB3    (*(reg32_t *)(CAN2_BASE_ADDR + 0x5C))
00915 
00916 
00917 /* MultiMedia Card Interface(MCI) Controller */
00918 #define MCI_BASE_ADDR       0xE008C000
00919 #define MCI_POWER      (*(reg32_t *)(MCI_BASE_ADDR + 0x00))
00920 #define MCI_CLOCK      (*(reg32_t *)(MCI_BASE_ADDR + 0x04))
00921 #define MCI_ARGUMENT   (*(reg32_t *)(MCI_BASE_ADDR + 0x08))
00922 #define MCI_COMMAND    (*(reg32_t *)(MCI_BASE_ADDR + 0x0C))
00923 #define MCI_RESP_CMD   (*(reg32_t *)(MCI_BASE_ADDR + 0x10))
00924 #define MCI_RESP0      (*(reg32_t *)(MCI_BASE_ADDR + 0x14))
00925 #define MCI_RESP1      (*(reg32_t *)(MCI_BASE_ADDR + 0x18))
00926 #define MCI_RESP2      (*(reg32_t *)(MCI_BASE_ADDR + 0x1C))
00927 #define MCI_RESP3      (*(reg32_t *)(MCI_BASE_ADDR + 0x20))
00928 #define MCI_DATA_TMR   (*(reg32_t *)(MCI_BASE_ADDR + 0x24))
00929 #define MCI_DATA_LEN   (*(reg32_t *)(MCI_BASE_ADDR + 0x28))
00930 #define MCI_DATA_CTRL  (*(reg32_t *)(MCI_BASE_ADDR + 0x2C))
00931 #define MCI_DATA_CNT   (*(reg32_t *)(MCI_BASE_ADDR + 0x30))
00932 #define MCI_STATUS     (*(reg32_t *)(MCI_BASE_ADDR + 0x34))
00933 #define MCI_CLEAR      (*(reg32_t *)(MCI_BASE_ADDR + 0x38))
00934 #define MCI_MASK0      (*(reg32_t *)(MCI_BASE_ADDR + 0x3C))
00935 #define MCI_MASK1      (*(reg32_t *)(MCI_BASE_ADDR + 0x40))
00936 #define MCI_FIFO_CNT   (*(reg32_t *)(MCI_BASE_ADDR + 0x48))
00937 #define MCI_FIFO       (*(reg32_t *)(MCI_BASE_ADDR + 0x80))
00938 
00939 
00940 /* I2S Interface Controller (I2S) */
00941 #define I2S_BASE_ADDR       0xE0088000
00942 #define I2S_DAO        (*(reg32_t *)(I2S_BASE_ADDR + 0x00))
00943 #define I2S_DAI        (*(reg32_t *)(I2S_BASE_ADDR + 0x04))
00944 #define I2S_TX_FIFO    (*(reg32_t *)(I2S_BASE_ADDR + 0x08))
00945 #define I2S_RX_FIFO    (*(reg32_t *)(I2S_BASE_ADDR + 0x0C))
00946 #define I2S_STATE      (*(reg32_t *)(I2S_BASE_ADDR + 0x10))
00947 #define I2S_DMA1       (*(reg32_t *)(I2S_BASE_ADDR + 0x14))
00948 #define I2S_DMA2       (*(reg32_t *)(I2S_BASE_ADDR + 0x18))
00949 #define I2S_IRQ        (*(reg32_t *)(I2S_BASE_ADDR + 0x1C))
00950 #define I2S_TXRATE     (*(reg32_t *)(I2S_BASE_ADDR + 0x20))
00951 #define I2S_RXRATE     (*(reg32_t *)(I2S_BASE_ADDR + 0x24))
00952 
00953 
00954 /* General-purpose DMA Controller */
00955 #define DMA_BASE_ADDR       0xFFE04000
00956 #define GPDMA_INT_STAT         (*(reg32_t *)(DMA_BASE_ADDR + 0x000))
00957 #define GPDMA_INT_TCSTAT       (*(reg32_t *)(DMA_BASE_ADDR + 0x004))
00958 #define GPDMA_INT_TCCLR        (*(reg32_t *)(DMA_BASE_ADDR + 0x008))
00959 #define GPDMA_INT_ERR_STAT     (*(reg32_t *)(DMA_BASE_ADDR + 0x00C))
00960 #define GPDMA_INT_ERR_CLR      (*(reg32_t *)(DMA_BASE_ADDR + 0x010))
00961 #define GPDMA_RAW_INT_TCSTAT   (*(reg32_t *)(DMA_BASE_ADDR + 0x014))
00962 #define GPDMA_RAW_INT_ERR_STAT (*(reg32_t *)(DMA_BASE_ADDR + 0x018))
00963 #define GPDMA_ENABLED_CHNS     (*(reg32_t *)(DMA_BASE_ADDR + 0x01C))
00964 #define GPDMA_SOFT_BREQ        (*(reg32_t *)(DMA_BASE_ADDR + 0x020))
00965 #define GPDMA_SOFT_SREQ        (*(reg32_t *)(DMA_BASE_ADDR + 0x024))
00966 #define GPDMA_SOFT_LBREQ       (*(reg32_t *)(DMA_BASE_ADDR + 0x028))
00967 #define GPDMA_SOFT_LSREQ       (*(reg32_t *)(DMA_BASE_ADDR + 0x02C))
00968 #define GPDMA_CONFIG           (*(reg32_t *)(DMA_BASE_ADDR + 0x030))
00969 #define GPDMA_SYNC             (*(reg32_t *)(DMA_BASE_ADDR + 0x034))
00970 
00971 /* DMA channel 0 registers */
00972 #define GPDMA_CH0_SRC      (*(reg32_t *)(DMA_BASE_ADDR + 0x100))
00973 #define GPDMA_CH0_DEST     (*(reg32_t *)(DMA_BASE_ADDR + 0x104))
00974 #define GPDMA_CH0_LLI      (*(reg32_t *)(DMA_BASE_ADDR + 0x108))
00975 #define GPDMA_CH0_CTRL     (*(reg32_t *)(DMA_BASE_ADDR + 0x10C))
00976 #define GPDMA_CH0_CFG      (*(reg32_t *)(DMA_BASE_ADDR + 0x110))
00977 
00978 /* DMA channel 1 registers */
00979 #define GPDMA_CH1_SRC      (*(reg32_t *)(DMA_BASE_ADDR + 0x120))
00980 #define GPDMA_CH1_DEST     (*(reg32_t *)(DMA_BASE_ADDR + 0x124))
00981 #define GPDMA_CH1_LLI      (*(reg32_t *)(DMA_BASE_ADDR + 0x128))
00982 #define GPDMA_CH1_CTRL     (*(reg32_t *)(DMA_BASE_ADDR + 0x12C))
00983 #define GPDMA_CH1_CFG      (*(reg32_t *)(DMA_BASE_ADDR + 0x130))
00984 
00985 
00986 /* USB Controller */
00987 #define USB_INT_BASE_ADDR   0xE01FC1C0
00988 #define USB_BASE_ADDR       0xFFE0C200      /* USB Base Address */
00989 
00990 #define USB_INT_STAT    (*(reg32_t *)(USB_INT_BASE_ADDR + 0x00))
00991 
00992 /* USB Device Interrupt Registers */
00993 #define DEV_INT_STAT    (*(reg32_t *)(USB_BASE_ADDR + 0x00))
00994 #define DEV_INT_EN      (*(reg32_t *)(USB_BASE_ADDR + 0x04))
00995 #define DEV_INT_CLR     (*(reg32_t *)(USB_BASE_ADDR + 0x08))
00996 #define DEV_INT_SET     (*(reg32_t *)(USB_BASE_ADDR + 0x0C))
00997 #define DEV_INT_PRIO    (*(reg32_t *)(USB_BASE_ADDR + 0x2C))
00998 
00999 /* USB Device Endpoint Interrupt Registers */
01000 #define EP_INT_STAT     (*(reg32_t *)(USB_BASE_ADDR + 0x30))
01001 #define EP_INT_EN       (*(reg32_t *)(USB_BASE_ADDR + 0x34))
01002 #define EP_INT_CLR      (*(reg32_t *)(USB_BASE_ADDR + 0x38))
01003 #define EP_INT_SET      (*(reg32_t *)(USB_BASE_ADDR + 0x3C))
01004 #define EP_INT_PRIO     (*(reg32_t *)(USB_BASE_ADDR + 0x40))
01005 
01006 /* USB Device Endpoint Realization Registers */
01007 #define REALIZE_EP      (*(reg32_t *)(USB_BASE_ADDR + 0x44))
01008 #define EP_INDEX        (*(reg32_t *)(USB_BASE_ADDR + 0x48))
01009 #define MAXPACKET_SIZE  (*(reg32_t *)(USB_BASE_ADDR + 0x4C))
01010 
01011 /* USB Device Command Reagisters */
01012 #define CMD_CODE        (*(reg32_t *)(USB_BASE_ADDR + 0x10))
01013 #define CMD_DATA        (*(reg32_t *)(USB_BASE_ADDR + 0x14))
01014 
01015 /* USB Device Data Transfer Registers */
01016 #define RX_DATA         (*(reg32_t *)(USB_BASE_ADDR + 0x18))
01017 #define TX_DATA         (*(reg32_t *)(USB_BASE_ADDR + 0x1C))
01018 #define RX_PLENGTH      (*(reg32_t *)(USB_BASE_ADDR + 0x20))
01019 #define TX_PLENGTH      (*(reg32_t *)(USB_BASE_ADDR + 0x24))
01020 #define USB_CTRL        (*(reg32_t *)(USB_BASE_ADDR + 0x28))
01021 
01022 /* USB Device DMA Registers */
01023 #define DMA_REQ_STAT        (*(reg32_t *)(USB_BASE_ADDR + 0x50))
01024 #define DMA_REQ_CLR         (*(reg32_t *)(USB_BASE_ADDR + 0x54))
01025 #define DMA_REQ_SET         (*(reg32_t *)(USB_BASE_ADDR + 0x58))
01026 #define UDCA_HEAD           (*(reg32_t *)(USB_BASE_ADDR + 0x80))
01027 #define EP_DMA_STAT         (*(reg32_t *)(USB_BASE_ADDR + 0x84))
01028 #define EP_DMA_EN           (*(reg32_t *)(USB_BASE_ADDR + 0x88))
01029 #define EP_DMA_DIS          (*(reg32_t *)(USB_BASE_ADDR + 0x8C))
01030 #define DMA_INT_STAT        (*(reg32_t *)(USB_BASE_ADDR + 0x90))
01031 #define DMA_INT_EN          (*(reg32_t *)(USB_BASE_ADDR + 0x94))
01032 #define EOT_INT_STAT        (*(reg32_t *)(USB_BASE_ADDR + 0xA0))
01033 #define EOT_INT_CLR         (*(reg32_t *)(USB_BASE_ADDR + 0xA4))
01034 #define EOT_INT_SET         (*(reg32_t *)(USB_BASE_ADDR + 0xA8))
01035 #define NDD_REQ_INT_STAT    (*(reg32_t *)(USB_BASE_ADDR + 0xAC))
01036 #define NDD_REQ_INT_CLR     (*(reg32_t *)(USB_BASE_ADDR + 0xB0))
01037 #define NDD_REQ_INT_SET     (*(reg32_t *)(USB_BASE_ADDR + 0xB4))
01038 #define SYS_ERR_INT_STAT    (*(reg32_t *)(USB_BASE_ADDR + 0xB8))
01039 #define SYS_ERR_INT_CLR     (*(reg32_t *)(USB_BASE_ADDR + 0xBC))
01040 #define SYS_ERR_INT_SET     (*(reg32_t *)(USB_BASE_ADDR + 0xC0))
01041 
01042 /* USB Host and OTG registers are for LPC24xx only */
01043 /* USB Host Controller */
01044 #define USBHC_BASE_ADDR     0xFFE0C000
01045 #define HC_REVISION         (*(reg32_t *)(USBHC_BASE_ADDR + 0x00))
01046 #define HC_CONTROL          (*(reg32_t *)(USBHC_BASE_ADDR + 0x04))
01047 #define HC_CMD_STAT         (*(reg32_t *)(USBHC_BASE_ADDR + 0x08))
01048 #define HC_INT_STAT         (*(reg32_t *)(USBHC_BASE_ADDR + 0x0C))
01049 #define HC_INT_EN           (*(reg32_t *)(USBHC_BASE_ADDR + 0x10))
01050 #define HC_INT_DIS          (*(reg32_t *)(USBHC_BASE_ADDR + 0x14))
01051 #define HC_HCCA             (*(reg32_t *)(USBHC_BASE_ADDR + 0x18))
01052 #define HC_PERIOD_CUR_ED    (*(reg32_t *)(USBHC_BASE_ADDR + 0x1C))
01053 #define HC_CTRL_HEAD_ED     (*(reg32_t *)(USBHC_BASE_ADDR + 0x20))
01054 #define HC_CTRL_CUR_ED      (*(reg32_t *)(USBHC_BASE_ADDR + 0x24))
01055 #define HC_BULK_HEAD_ED     (*(reg32_t *)(USBHC_BASE_ADDR + 0x28))
01056 #define HC_BULK_CUR_ED      (*(reg32_t *)(USBHC_BASE_ADDR + 0x2C))
01057 #define HC_DONE_HEAD        (*(reg32_t *)(USBHC_BASE_ADDR + 0x30))
01058 #define HC_FM_INTERVAL      (*(reg32_t *)(USBHC_BASE_ADDR + 0x34))
01059 #define HC_FM_REMAINING     (*(reg32_t *)(USBHC_BASE_ADDR + 0x38))
01060 #define HC_FM_NUMBER        (*(reg32_t *)(USBHC_BASE_ADDR + 0x3C))
01061 #define HC_PERIOD_START     (*(reg32_t *)(USBHC_BASE_ADDR + 0x40))
01062 #define HC_LS_THRHLD        (*(reg32_t *)(USBHC_BASE_ADDR + 0x44))
01063 #define HC_RH_DESCA         (*(reg32_t *)(USBHC_BASE_ADDR + 0x48))
01064 #define HC_RH_DESCB         (*(reg32_t *)(USBHC_BASE_ADDR + 0x4C))
01065 #define HC_RH_STAT          (*(reg32_t *)(USBHC_BASE_ADDR + 0x50))
01066 #define HC_RH_PORT_STAT1    (*(reg32_t *)(USBHC_BASE_ADDR + 0x54))
01067 #define HC_RH_PORT_STAT2    (*(reg32_t *)(USBHC_BASE_ADDR + 0x58))
01068 
01069 /* USB OTG Controller */
01070 #define USBOTG_BASE_ADDR    0xFFE0C100
01071 #define OTG_INT_STAT        (*(reg32_t *)(USBOTG_BASE_ADDR + 0x00))
01072 #define OTG_INT_EN          (*(reg32_t *)(USBOTG_BASE_ADDR + 0x04))
01073 #define OTG_INT_SET         (*(reg32_t *)(USBOTG_BASE_ADDR + 0x08))
01074 #define OTG_INT_CLR         (*(reg32_t *)(USBOTG_BASE_ADDR + 0x0C))
01075 /* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ 
01076 #define OTG_STAT_CTRL       (*(reg32_t *)(USBOTG_BASE_ADDR + 0x10))
01077 #define OTG_TIMER           (*(reg32_t *)(USBOTG_BASE_ADDR + 0x14))
01078 
01079 #define USBOTG_I2C_BASE_ADDR    0xFFE0C300
01080 #define OTG_I2C_RX          (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x00))
01081 #define OTG_I2C_TX          (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x00))
01082 #define OTG_I2C_STS         (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x04))
01083 #define OTG_I2C_CTL         (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x08))
01084 #define OTG_I2C_CLKHI       (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x0C))
01085 #define OTG_I2C_CLKLO       (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x10))
01086 
01087 /* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are 
01088 OTG_CLK_CTRL and OTG_CLK_STAT respectively. */
01089 #define USBOTG_CLK_BASE_ADDR    0xFFE0CFF0
01090 #define OTG_CLK_CTRL        (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x04))
01091 #define OTG_CLK_STAT        (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x08))
01092 
01093 /* Note: below three register name convention is for LPC23xx USB device only, match
01094 with the spec. update in USB Device Section. */ 
01095 #define USBPortSel          (*(reg32_t *)(USBOTG_BASE_ADDR + 0x10))
01096 #define USBClkCtrl          (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x04))
01097 #define USBClkSt            (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x08))
01098 
01099 /* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
01100 #define MAC_BASE_ADDR       0xFFE00000 /* AHB Peripheral # 0 */
01101 #define MAC_MAC1            (*(reg32_t *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
01102 #define MAC_MAC2            (*(reg32_t *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
01103 #define MAC_IPGT            (*(reg32_t *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
01104 #define MAC_IPGR            (*(reg32_t *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */
01105 #define MAC_CLRT            (*(reg32_t *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */
01106 #define MAC_MAXF            (*(reg32_t *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */
01107 #define MAC_SUPP            (*(reg32_t *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */
01108 #define MAC_TEST            (*(reg32_t *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */
01109 #define MAC_MCFG            (*(reg32_t *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */
01110 #define MAC_MCMD            (*(reg32_t *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */
01111 #define MAC_MADR            (*(reg32_t *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */
01112 #define MAC_MWTD            (*(reg32_t *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
01113 #define MAC_MRDD            (*(reg32_t *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
01114 #define MAC_MIND            (*(reg32_t *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */
01115 
01116 #define MAC_SA0             (*(reg32_t *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */
01117 #define MAC_SA1             (*(reg32_t *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */
01118 #define MAC_SA2             (*(reg32_t *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */
01119 
01120 #define MAC_COMMAND         (*(reg32_t *)(MAC_BASE_ADDR + 0x100)) /* Command reg */
01121 #define MAC_STATUS          (*(reg32_t *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */
01122 #define MAC_RXDESCRIPTOR    (*(reg32_t *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */
01123 #define MAC_RXSTATUS        (*(reg32_t *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */
01124 #define MAC_RXDESCRIPTORNUM (*(reg32_t *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */
01125 #define MAC_RXPRODUCEINDEX  (*(reg32_t *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */
01126 #define MAC_RXCONSUMEINDEX  (*(reg32_t *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */
01127 #define MAC_TXDESCRIPTOR    (*(reg32_t *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */
01128 #define MAC_TXSTATUS        (*(reg32_t *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */
01129 #define MAC_TXDESCRIPTORNUM (*(reg32_t *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */
01130 #define MAC_TXPRODUCEINDEX  (*(reg32_t *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */
01131 #define MAC_TXCONSUMEINDEX  (*(reg32_t *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */
01132 
01133 #define MAC_TSV0            (*(reg32_t *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */
01134 #define MAC_TSV1            (*(reg32_t *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */
01135 #define MAC_RSV             (*(reg32_t *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */
01136 
01137 #define MAC_FLOWCONTROLCNT  (*(reg32_t *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */
01138 #define MAC_FLOWCONTROLSTS  (*(reg32_t *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */
01139 
01140 #define MAC_RXFILTERCTRL    (*(reg32_t *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */
01141 #define MAC_RXFILTERWOLSTS  (*(reg32_t *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */
01142 #define MAC_RXFILTERWOLCLR  (*(reg32_t *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */
01143 
01144 #define MAC_HASHFILTERL     (*(reg32_t *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */
01145 #define MAC_HASHFILTERH     (*(reg32_t *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */
01146 
01147 #define MAC_INTSTATUS       (*(reg32_t *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */
01148 #define MAC_INTENABLE       (*(reg32_t *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg  */
01149 #define MAC_INTCLEAR        (*(reg32_t *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */
01150 #define MAC_INTSET          (*(reg32_t *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */
01151 
01152 #define MAC_POWERDOWN       (*(reg32_t *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */
01153 #define MAC_MODULEID        (*(reg32_t *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
01154 
01155 #endif /* LPC23XX_H */