ser_lm3s.h

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#ifndef SER_LM3S_H
#define SER_LM3S_H

#include <cfg/cfg_debug.h>
#include <cpu/power.h> /* cpu_relax() */
#include <drv/clock_lm3s.h> /* lm3s_busyWait() */
#include <io/lm3s.h>

/* Serial hardware numbers */
enum
{
    SER_UART0,
    SER_UART1,
    SER_UART2,

    SER_CNT //< Number of serial ports
};

/* Software errors */
#define SERRF_RXFIFOOVERRUN  BV(0) //< Rx FIFO buffer overrun
#define SERRF_RXTIMEOUT      BV(1) //< Receive timeout
#define SERRF_TXTIMEOUT      BV(2) //< Transmit timeout

/*
 * Hardware errors.
 */
#define SERRF_RXSROVERRUN    0 //< Input overrun
#define SERRF_FRAMEERROR     0 //< Stop bit missing
#define SERRF_PARITYERROR    0 //< Parity error
#define SERRF_NOISEERROR     0 //< Noise error

/* Serial error/status flags */
typedef uint32_t serstatus_t;

INLINE void lm3s_uartDisable(uint32_t base)
{
    /* Disable the hardware FIFO */
    HWREG(base + UART_O_LCRH) &= ~UART_LCRH_FEN;

    /* Disable the UART */
    HWREG(base + UART_O_CTL) &=
        ~(UART_CTL_UARTEN | UART_CTL_TXE | UART_CTL_RXE);
    lm3s_busyWait(512);
}

INLINE void lm3s_uartEnable(uint32_t base)
{
    /* Enable the hardware FIFO */
    HWREG(base + UART_O_LCRH) |= UART_LCRH_FEN;

    /* Enable RX, TX, and the UART */
    HWREG(base + UART_O_CTL) |=
            UART_CTL_UARTEN | UART_CTL_TXE | UART_CTL_RXE;
    lm3s_busyWait(512);
}

/* Clear the flags register */
INLINE void lm3s_uartClear(uint32_t base)
{
    HWREG(base + UART_O_FR) = 0;
}

INLINE bool lm3s_uartTxDone(uint32_t base)
{
    return HWREG(base + UART_O_FR) & UART_FR_TXFE ? true : false;
}

INLINE bool lm3s_uartTxReady(uint32_t base)
{
    return HWREG(base + UART_O_FR) & UART_FR_TXFF ? false : true;
}

INLINE bool lm3s_uartRxReady(uint32_t base)
{
    return HWREG(base + UART_O_FR) & UART_FR_RXFE ? false : true;
}

INLINE bool lm3s_uartReady(uint32_t base)
{
    return HWREG(base + UART_O_FR) & UART_FR_BUSY ? false : true;
}

INLINE int lm3s_uartPutCharNonBlocking(uint32_t base, unsigned char c)
{
    if (!lm3s_uartTxReady(base))
        return EOF;
    HWREG(base + UART_O_DR) = c;
    return c;
}

INLINE int lm3s_uartPutChar(uint32_t base, unsigned char c)
{
    while (!lm3s_uartTxReady(base))
        cpu_relax();
    HWREG(base + UART_O_DR) = c;
    return c;
}

INLINE int lm3s_uartGetCharNonBlocking(uint32_t base)
{
    if (!lm3s_uartRxReady(base))
        return EOF;
    return HWREG(base + UART_O_DR);
}

INLINE int lm3s_uartGetChar(uint32_t base)
{
    while (!lm3s_uartRxReady(base))
        cpu_relax();
    return HWREG(base + UART_O_DR);
}

void lm3s_uartSetBaudRate(uint32_t base, unsigned long baud);
void lm3s_uartSetParity(uint32_t base, int parity);
void lm3s_uartInit(int port);

#endif /* SER_LM3S_H */