stm32_memmap.h

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00001 
00036 #ifndef STM32_MEMMAP_H
00037 #define STM32_MEMMAP_H
00038 
00039 /* Peripheral and SRAM base address in the alias region */
00040 #define PERIPH_BB_BASE        (0x42000000)
00041 #define SRAM_BB_BASE          (0x22000000)
00042 
00043 /* Peripheral and SRAM base address in the bit-band region */
00044 #define SRAM_BASE             (0x20000000)
00045 #define PERIPH_BASE           (0x40000000)
00046 
00047 /* Flash refisters base address */
00048 #define FLASH_BASE            (0x40022000)
00049 /* Flash Option Bytes base address */
00050 #define OB_BASE               (0x1FFFF800)
00051 
00052 /* Peripheral memory map */
00053 #define APB1PERIPH_BASE       (PERIPH_BASE)
00054 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
00055 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
00056 
00057 #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
00058 #define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
00059 #define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
00060 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
00061 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
00062 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
00063 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
00064 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
00065 #define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
00066 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
00067 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
00068 #define CAN_BASE              (APB1PERIPH_BASE + 0x6400)
00069 #define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)
00070 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
00071 
00072 #define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)
00073 #define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
00074 #define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)
00075 #define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)
00076 #define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)
00077 #define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)
00078 #define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)
00079 #define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
00080 #define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)
00081 #define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)
00082 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
00083 #define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
00084 
00085 #define DMA_BASE              (AHBPERIPH_BASE + 0x0000)
00086 #define DMA_CHANNEL1_BASE     (AHBPERIPH_BASE + 0x0008)
00087 #define DMA_CHANNEL2_BASE     (AHBPERIPH_BASE + 0x001C)
00088 #define DMA_CHANNEL3_BASE     (AHBPERIPH_BASE + 0x0030)
00089 #define DMA_CHANNEL4_BASE     (AHBPERIPH_BASE + 0x0044)
00090 #define DMA_CHANNEL5_BASE     (AHBPERIPH_BASE + 0x0058)
00091 #define DMA_CHANNEL6_BASE     (AHBPERIPH_BASE + 0x006C)
00092 #define DMA_CHANNEL7_BASE     (AHBPERIPH_BASE + 0x0080)
00093 #define RCC_BASE              (AHBPERIPH_BASE + 0x1000)
00094 
00095 /* System Control Space memory map */
00096 #define SCS_BASE              (0xE000E000)
00097 
00098 #define SYSTICK_BASE          (SCS_BASE + 0x0010)
00099 #define NVIC_BASE             (SCS_BASE + 0x0100)
00100 #define SCB_BASE              (SCS_BASE + 0x0D00)
00101 
00102 #endif /* STM32_MEMMAP_H */