at91_dbgu.h

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00001 
00040 /*
00041  * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
00042  *
00043  * Redistribution and use in source and binary forms, with or without
00044  * modification, are permitted provided that the following conditions
00045  * are met:
00046  *
00047  * 1. Redistributions of source code must retain the above copyright
00048  *    notice, this list of conditions and the following disclaimer.
00049  * 2. Redistributions in binary form must reproduce the above copyright
00050  *    notice, this list of conditions and the following disclaimer in the
00051  *    documentation and/or other materials provided with the distribution.
00052  * 3. Neither the name of the copyright holders nor the names of
00053  *    contributors may be used to endorse or promote products derived
00054  *    from this software without specific prior written permission.
00055  *
00056  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00057  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00058  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00059  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00060  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00061  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00062  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00063  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00064  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00065  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00066  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00067  * SUCH DAMAGE.
00068  *
00069  * For additional information see http://www.ethernut.de/
00070  */
00071 #ifndef AT91_DBGU_H
00072 #define AT91_DBGU_H
00073 
00074 #define DBGU_CR     (*((reg32_t *)(DBGU_BASE + US_CR_OFF)))     ///<DBGU control register address.
00075 #define DBGU_MR     (*((reg32_t *)(DBGU_BASE + US_MR_OFF)))     ///<DBGU mode register address.
00076 #define DBGU_IER    (*((reg32_t *)(DBGU_BASE + US_IER_OFF)))    ///<DBGU interrupt enable register address.
00077 #define DBGU_IDR    (*((reg32_t *)(DBGU_BASE + US_IDR_OFF)))    ///<DBGU interrupt disable register address.
00078 #define DBGU_IMR    (*((reg32_t *)(DBGU_BASE + US_IMR_OFF)))    ///<DBGU interrupt mask register address.
00079 #define DBGU_SR     (*((reg32_t *)(DBGU_BASE + US_CSR_OFF)))    ///<DBGU status register address.
00080 #define DBGU_RHR    (*((reg32_t *)(DBGU_BASE + US_RHR_OFF)))    ///<DBGU receiver holding register address.
00081 #define DBGU_THR    (*((reg32_t *)(DBGU_BASE + US_THR_OFF)))    ///<DBGU transmitter holding register address.
00082 #define DBGU_BRGR   (*((reg32_t *)(DBGU_BASE + US_BRGR_OFF)))   ///<DBGU baud rate register address.
00083 
00084 #define DBGU_CIDR_OFF           0x00000040      ///<DBGU chip ID register offset.
00085 #define DBGU_CIDR   (*((reg32_t *)(DBGU_BASE + DBGU_CIDR_OFF))) ///<DBGU chip ID register.
00086 
00087 #define DBGU_EXID_OFF           0x00000044      ///<DBGU chip ID extension register offset.
00088 #define DBGU_EXID   (*((reg32_t *)(DBGU_BASE + DBGU_EXID_OFF))) ///<DBGU chip ID extension register.
00089 
00090 #define DBGU_FNR_OFF            0x00000048      ///<DBGU force NTRST register offset.
00091 #define DBGU_FNR    (*((reg32_t *)(DBGU_BASE + DBGU_FNR_OFF)))  ///<DBGU force NTRST register.
00092 
00093 #if defined(DBGU_HAS_PDC)
00094 #define DBGU_RPR    (*((reg32_t *)(DBGU_BASE + PERIPH_RPR_OFF)))    ///<PDC receive pointer register.
00095 #define DBGU_RCR    (*((reg32_t *)(DBGU_BASE + PERIPH_RCR_OFF)))    ///<PDC receive counter register.
00096 #define DBGU_TPR    (*((reg32_t *)(DBGU_BASE + PERIPH_TPR_OFF)))    ///<PDC transmit pointer register.
00097 #define DBGU_TCR    (*((reg32_t *)(DBGU_BASE + PERIPH_TCR_OFF)))    ///<PDC transmit counter register.
00098 #define DBGU_RNPR   (*((reg32_t *)(DBGU_BASE + PERIPH_RNPR_OFF)))   ///<PDC receive next pointer register.
00099 #define DBGU_RNCR   (*((reg32_t *)(DBGU_BASE + PERIPH_RNCR_OFF)))   ///<PDC receive next counter register.
00100 #define DBGU_TNPR   (*((reg32_t *)(DBGU_BASE + PERIPH_TNPR_OFF)))   ///<PDC transmit next pointer register.
00101 #define DBGU_TNCR   (*((reg32_t *)(DBGU_BASE + PERIPH_TNCR_OFF)))   ///<PDC transmit next counter register.
00102 #define DBGU_PTCR   (*((reg32_t *)(DBGU_BASE + PERIPH_PTCR_OFF)))   ///<PDC transfer control register.
00103 #define DBGU_PTSR   (*((reg32_t *)(DBGU_BASE + PERIPH_PTSR_OFF)))   ///<PDC transfer status register.
00104 #endif
00105 
00106 #endif /* AT91_DBGU_H */