at91_us.h File Reference

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Defines
#define	US_CR_OFF   0x00000000
	USART Control Register.
#define	US0_CR   (*((reg32_t *)(USART0_BASE + US_CR_OFF)))
	Channel 0 control register address.
#define	US1_CR   (*((reg32_t *)(USART1_BASE + US_CR_OFF)))
	Channel 1 control register address.
#define	US_RSTRX   2
	Reset receiver.
#define	US_RSTTX   3
	Reset transmitter.
#define	US_RXEN   4
	Receiver enable.
#define	US_RXDIS   5
	Receiver disable.
#define	US_TXEN   6
	Transmitter enable.
#define	US_TXDIS   7
	Transmitter disable.
#define	US_RSTSTA   8
	Reset status bits.
#define	US_STTBRK   9
	Start break.
#define	US_STPBRK   10
	Stop break.
#define	US_STTTO   11
	Start timeout.
#define	US_SENDA   12
	Send next byte with address bit set.
#define	US_RSTIT   13
	Reset interations.
#define	US_RSTNAK   14
	Reset non acknowledge.
#define	US_RETTO   15
	Rearm time out.
#define	US_DTREN   16
	Data terminal ready enable.
#define	US_DTRDIS   17
	Data terminal ready disable.
#define	US_RTSEN   18
	Request to send enable.
#define	US_RTSDIS   19
	Request to send disable.
#define	US_MR_OFF   0x00000004
	Mode Register.
#define	US0_MR   (*((reg32_t *)(USART0_BASE + US_MR_OFF)))
	Channel 0 mode register address.
#define	US1_MR   (*((reg32_t *)(USART1_BASE + US_MR_OFF)))
	Channel 1 mode register address.
#define	US_USART_MODE_MASK   0x0000000F
	USART mode mask.
#define	US_USART_MODE_NORMA   0x00000000
	Normal.
#define	US_USART_MODE_RS485   0x00000001
	RS485.
#define	US_USART_MODE_HW_HDSH   0x00000002
	Hardware handshaking.
#define	US_USART_MODE_MODEM   0x00000003
	Modem.
#define	US_USART_MODE_ISO7816T0   0x00000004
	ISO7816 protocol: T=0.
#define	US_USART_MODE_ISO7816T1   0x00000006
	ISO7816 protocol: T=1.
#define	US_USART_MODE_IRDA   0x00000008
	IrDA.
#define	US_CLKS_MASK   0x00000030
	Clock selection mask.
#define	US_CLKS_MCK   0x00000000
	Master clock.
#define	US_CLKS_MCK8   0x00000010
	Master clock divided by 8.
#define	US_CLKS_SCK   0x00000020
	External clock.
#define	US_CLKS_SLCK   0x00000030
	Slow clock.
#define	US_CHRL_MASK   0x000000C0
	Masks data length.
#define	US_CHRL_5   0x00000000
	5 data bits.
#define	US_CHRL_6   0x00000040
	6 data bits.
#define	US_CHRL_7   0x00000080
	7 data bits.
#define	US_CHRL_8   0x000000C0
	8 data bits.
#define	US_SYNC   8
	Synchronous mode enable.
#define	US_PAR_MASK   0x00000E00
	Parity mode mask.
#define	US_PAR_EVEN   0x00000000
	Even parity.
#define	US_PAR_ODD   0x00000200
	Odd parity.
#define	US_PAR_SPACE   0x00000400
	Space parity.
#define	US_PAR_MARK   0x00000600
	Marked parity.
#define	US_PAR_NO   0x00000800
	No parity.
#define	US_PAR_MULTIDROP   0x00000C00
	Multi-drop mode.
#define	US_NBSTOP_MASK   0x00003000
	Masks stop bit length.
#define	US_NBSTOP_1   0x00000000
	1 stop bit.
#define	US_NBSTOP_1_5   0x00001000
	1.5 stop bits.
#define	US_NBSTOP_2   0x00002000
	2 stop bits.
#define	US_CHMODE_MASK   0x0000C000
	Channel mode mask.
#define	US_CHMODE_NORMAL   0x00000000
	Normal mode.
#define	US_CHMODE_AUTOMATIC_ECHO   0x00004000
	Automatic echo.
#define	US_CHMODE_LOCAL_LOOPBACK   0x00008000
	Local loopback.
#define	US_CHMODE_REMOTE_LOOPBACK   0x0000C000
	Remote loopback.
#define	US_MSBF   16
	Bit order.
#define	US_MODE9   17
	9 bit mode.
#define	US_CLKO   18
	Clock output select.
#define	US_OVER   19
	Oversampling mode.
#define	US_INACK   20
	Inhibit non acknowledge.
#define	US_DSNACK   21
	Disable successive nack.
#define	US_MAX_INTERATION_MASK   0x07000000
	Max numer of interation in mode ISO7816 T=0.
#define	US_FILTER   28
	Infrared receive line filter.
#define	US_IER_OFF   0x00000008
	Status and Interrupt Register.
#define	US0_IER   (*((reg32_t *)(USART0_BASE + US_IER_OFF)))
	Channel 0 interrupt enable register address.
#define	US1_IER   (*((reg32_t *)(USART1_BASE + US_IER_OFF)))
	Channel 1 interrupt enable register address.
#define	US_IDR_OFF   0x0000000C
	USART interrupt disable register offset.
#define	US0_IDR   (*((reg32_t *)(USART0_BASE + US_IDR_OFF)))
	Channel 0 interrupt disable register address.
#define	US1_IDR   (*((reg32_t *)(USART1_BASE + US_IDR_OFF)))
	Channel 1 interrupt disable register address.
#define	US_IMR_OFF   0x00000010
	USART interrupt mask register offset.
#define	US0_IMR   (*((reg32_t *)(USART0_BASE + US_IMR_OFF)))
	Channel 0 interrupt mask register address.
#define	US1_IMR   (*((reg32_t *)(USART1_BASE + US_IMR_OFF)))
	Channel 1 interrupt mask register address.
#define	US_CSR_OFF   0x00000014
	USART status register offset.
#define	US0_CSR   (*((reg32_t *)(USART0_BASE + US_CSR_OFF)))
	Channel 0 status register address.
#define	US1_CSR   (*((reg32_t *)(USART1_BASE + US_CSR_OFF)))
	Channel 1 status register address.
#define	US_CSR_RI   20
	Image of RI input.
#define	US_CSR_DSR   21
	Image of DSR input.
#define	US_CSR_DCD   22
	Image of DCD input.
#define	US_CSR_CTS   23
	Image of CTS input.
#define	US_RXRDY   0
	Receiver ready.
#define	US_TXRDY   1
	Transmitter ready.
#define	US_RXBRK   2
	Receiver break.
#define	US_ENDRX   3
	End of receiver PDC transfer.
#define	US_ENDTX   4
	End of transmitter PDC transfer.
#define	US_OVRE   5
	Overrun error.
#define	US_FRAME   6
	Framing error.
#define	US_PARE   7
	Parity error.
#define	US_TIMEOUT   8
	Receiver timeout.
#define	US_TXEMPTY   9
	Transmitter empty.
#define	US_ITERATION   10
	Iteration interrupt enable.
#define	US_TXBUFE   11
	Buffer empty interrupt enable.
#define	US_RXBUFF   12
	Buffer full interrupt enable.
#define	US_NACK   13
	Non acknowledge interrupt enable.
#define	US_RIIC   16
	Ring indicator input change enable.
#define	US_DSRIC   17
	Data set ready input change enable.
#define	US_DCDIC   18
	Data carrier detect input change interrupt enable.
#define	US_CTSIC   19
	Clear to send input change interrupt enable.
#define	US_RHR_OFF   0x00000018
	Receiver Holding Register.
#define	US0_RHR   (*((reg32_t *)(USART0_BASE + US_RHR_OFF)))
	Channel 0 receiver holding register address.
#define	US1_RHR   (*((reg32_t *)(USART1_BASE + US_RHR_OFF)))
	Channel 1 receiver holding register address.
#define	US_RHR_RXCHR_MASK   0x000001FF
	Last char received if US_RXRDY is set.
#define	US_RHR_RXSYNH   15
	Received sync.
#define	US_THR_OFF   0x0000001C
	Transmitter Holding Register.
#define	US0_THR   (*((reg32_t *)(USART0_BASE + US_THR_OFF)))
	Channel 0 transmitter holding register address.
#define	US1_THR   (*((reg32_t *)(USART1_BASE + US_THR_OFF)))
	Channel 1 transmitter holding register address.
#define	US_THR_TXCHR_MASK   0x000001FF
	Next char to be trasmitted.
#define	US_THR_TXSYNH   15
	Sync field to be trasmitted.
#define	US_BRGR_OFF   0x00000020
	Baud Rate Generator Register.
#define	US0_BRGR   (*((reg32_t *)(USART0_BASE + US_BRGR_OFF)))
	Channel 0 baud rate register address.
#define	US1_BRGR   (*((reg32_t *)(USART1_BASE + US_BRGR_OFF)))
	Channel 1 baud rate register address.
#define	US_RTOR_OFF   0x00000024
	Receiver Timeout Register.
#define	US0_RTOR   (*((reg32_t *)(USART0_BASE + US_RTOR_OFF)))
	Channel 0 receiver timeout register address.
#define	US1_RTOR   (*((reg32_t *)(USART1_BASE + US_RTOR_OFF)))
	Channel 1 receiver timeout register address.
#define	US_TTGR_OFF   0x00000028
	Transmitter Time Guard Register.
#define	US0_TTGR   (*((reg32_t *)(USART0_BASE + US_TTGR_OFF)))
	Channel 0 transmitter time guard register address.
#define	US1_TTGR   (*((reg32_t *)(USART1_BASE + US_TTGR_OFF)))
	Channel 1 transmitter time guard register address.
#define	US_FIDI_OFF   0x00000040
	FI DI Ratio Register.
#define	US0_FIDI   (*((reg32_t *)(USART0_BASE + US_FIDI_OFF)))
	Channel 0 FI DI ratio register address.
#define	US1_FIDI   (*((reg32_t *)(USART1_BASE + US_FIDI_OFF)))
	Channel 1 FI DI ratio register address.
#define	US_NER_OFF   0x00000044
	Error Counter Register.
#define	US0_NER   (*((reg32_t *)(USART0_BASE + US_NER_OFF)))
	Channel 0 error counter register address.
#define	US1_NER   (*((reg32_t *)(USART1_BASE + US_NER_OFF)))
	Channel 1 error counter register address.
#define	US_IF_OFF   0x0000004C
	IrDA Filter Register.
#define	US0_IF   (*((reg32_t *)(USART0_BASE + US_IF_OFF)))
	Channel 0 IrDA filter register address.
#define	US1_IF   (*((reg32_t *)(USART1_BASE + US_IF_OFF)))
	Channel 1 IrDA filter register address.

---

Detailed Description

Author:

Daniele Basile <asterix@develer.com>

AT91 UART User interface. This file is based on NUT/OS implementation. See license below.

Definition in file at91_us.h.

---

Define Documentation

#define US_BRGR_OFF   0x00000020

Baud Rate Generator Register.

USART baud rate register offset.

Definition at line 233 of file at91_us.h.

#define US_CR_OFF   0x00000000

USART Control Register.

USART control register offset.

Definition at line 78 of file at91_us.h.

#define US_FIDI_OFF   0x00000040

FI DI Ratio Register.

USART FI DI ratio register offset.

Definition at line 260 of file at91_us.h.

#define US_IER_OFF   0x00000008

Status and Interrupt Register.

USART interrupt enable register offset.

Definition at line 168 of file at91_us.h.

#define US_IF_OFF   0x0000004C

IrDA Filter Register.

USART IrDA filter register offset.

Definition at line 278 of file at91_us.h.

#define US_MR_OFF   0x00000004

Mode Register.

USART mode register offset.

Definition at line 105 of file at91_us.h.

#define US_NER_OFF   0x00000044

Error Counter Register.

USART error counter register offset.

Definition at line 269 of file at91_us.h.

#define US_RHR_OFF   0x00000018

Receiver Holding Register.

USART receiver holding register offset.

Definition at line 211 of file at91_us.h.

#define US_RTOR_OFF   0x00000024

Receiver Timeout Register.

USART receiver timeout register offset.

Definition at line 242 of file at91_us.h.

#define US_THR_OFF   0x0000001C

Transmitter Holding Register.

USART transmitter holding register offset.

Definition at line 222 of file at91_us.h.

#define US_TTGR_OFF   0x00000028

Transmitter Time Guard Register.

USART transmitter time guard register offset.

Definition at line 251 of file at91_us.h.