lm3s_nvic.h
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00036 #ifndef LM3S_NVIC_H
00037 #define LM3S_NVIC_H
00038
00042
00043 #define NVIC_INT_TYPE 0xE000E004 ///< Interrupt Controller Type Reg
00044 #define NVIC_ST_CTRL 0xE000E010 ///< SysTick Control and Status Reg
00045 #define NVIC_ST_RELOAD 0xE000E014 ///< SysTick Reload Value Register
00046 #define NVIC_ST_CURRENT 0xE000E018 ///< SysTick Current Value Register
00047 #define NVIC_ST_CAL 0xE000E01C ///< SysTick Calibration Value Reg
00048 #define NVIC_EN0 0xE000E100 ///< IRQ 0 to 31 Set Enable Register
00049 #define NVIC_EN1 0xE000E104 ///< IRQ 32 to 63 Set Enable Register
00050 #define NVIC_DIS0 0xE000E180 ///< IRQ 0 to 31 Clear Enable Reg
00051 #define NVIC_DIS1 0xE000E184 ///< IRQ 32 to 63 Clear Enable Reg
00052 #define NVIC_PEND0 0xE000E200 ///< IRQ 0 to 31 Set Pending Register
00053 #define NVIC_PEND1 0xE000E204 ///< IRQ 32 to 63 Set Pending Reg
00054 #define NVIC_UNPEND0 0xE000E280 ///< IRQ 0 to 31 Clear Pending Reg
00055 #define NVIC_UNPEND1 0xE000E284 ///< IRQ 32 to 63 Clear Pending Reg
00056 #define NVIC_ACTIVE0 0xE000E300 ///< IRQ 0 to 31 Active Register
00057 #define NVIC_ACTIVE1 0xE000E304 ///< IRQ 32 to 63 Active Register
00058 #define NVIC_PRI0 0xE000E400 ///< IRQ 0 to 3 Priority Register
00059 #define NVIC_PRI1 0xE000E404 ///< IRQ 4 to 7 Priority Register
00060 #define NVIC_PRI2 0xE000E408 ///< IRQ 8 to 11 Priority Register
00061 #define NVIC_PRI3 0xE000E40C ///< IRQ 12 to 15 Priority Register
00062 #define NVIC_PRI4 0xE000E410 ///< IRQ 16 to 19 Priority Register
00063 #define NVIC_PRI5 0xE000E414 ///< IRQ 20 to 23 Priority Register
00064 #define NVIC_PRI6 0xE000E418 ///< IRQ 24 to 27 Priority Register
00065 #define NVIC_PRI7 0xE000E41C ///< IRQ 28 to 31 Priority Register
00066 #define NVIC_PRI8 0xE000E420 ///< IRQ 32 to 35 Priority Register
00067 #define NVIC_PRI9 0xE000E424 ///< IRQ 36 to 39 Priority Register
00068 #define NVIC_PRI10 0xE000E428 ///< IRQ 40 to 43 Priority Register
00069 #define NVIC_PRI11 0xE000E42C ///< IRQ 44 to 47 Priority Register
00070 #define NVIC_PRI12 0xE000E430 ///< IRQ 48 to 51 Priority Register
00071 #define NVIC_PRI13 0xE000E434 ///< IRQ 52 to 55 Priority Register
00072 #define NVIC_CPUID 0xE000ED00 ///< CPUID Base Register
00073 #define NVIC_INT_CTRL 0xE000ED04 ///< Interrupt Control State Register
00074 #define NVIC_VTABLE 0xE000ED08 ///< Vector Table Offset Register
00075 #define NVIC_APINT 0xE000ED0C ///< App. Int & Reset Control Reg
00076 #define NVIC_SYS_CTRL 0xE000ED10 ///< System Control Register
00077 #define NVIC_CFG_CTRL 0xE000ED14 ///< Configuration Control Register
00078 #define NVIC_SYS_PRI1 0xE000ED18 ///< Sys. Handlers 4 to 7 Priority
00079 #define NVIC_SYS_PRI2 0xE000ED1C ///< Sys. Handlers 8 to 11 Priority
00080 #define NVIC_SYS_PRI3 0xE000ED20 ///< Sys. Handlers 12 to 15 Priority
00081 #define NVIC_SYS_HND_CTRL 0xE000ED24 ///< System Handler Control and State
00082 #define NVIC_FAULT_STAT 0xE000ED28 ///< Configurable Fault Status Reg
00083 #define NVIC_HFAULT_STAT 0xE000ED2C ///< Hard Fault Status Register
00084 #define NVIC_DEBUG_STAT 0xE000ED30 ///< Debug Status Register
00085 #define NVIC_MM_ADDR 0xE000ED34 ///< Mem Manage Address Register
00086 #define NVIC_FAULT_ADDR 0xE000ED38 ///< Bus Fault Address Register
00087 #define NVIC_MPU_TYPE 0xE000ED90 ///< MPU Type Register
00088 #define NVIC_MPU_CTRL 0xE000ED94 ///< MPU Control Register
00089 #define NVIC_MPU_NUMBER 0xE000ED98 ///< MPU Region Number Register
00090 #define NVIC_MPU_BASE 0xE000ED9C ///< MPU Region Base Address Register
00091 #define NVIC_MPU_ATTR 0xE000EDA0 ///< MPU Region Attribute & Size Reg
00092 #define NVIC_DBG_CTRL 0xE000EDF0 ///< Debug Control and Status Reg
00093 #define NVIC_DBG_XFER 0xE000EDF4 ///< Debug Core Reg. Transfer Select
00094 #define NVIC_DBG_DATA 0xE000EDF8 ///< Debug Core Register Data
00095 #define NVIC_DBG_INT 0xE000EDFC ///< Debug Reset Interrupt Control
00096 #define NVIC_SW_TRIG 0xE000EF00 ///< Software Trigger Interrupt Reg
00097
00098
00102
00103 #define NVIC_INT_TYPE_LINES_M 0x0000001F ///< Number of interrupt lines (x32)
00104 #define NVIC_INT_TYPE_LINES_S 0
00105
00106
00110
00111 #define NVIC_ST_CTRL_COUNT 0x00010000 ///< Count flag
00112 #define NVIC_ST_CTRL_CLK_SRC 0x00000004 ///< Clock Source
00113 #define NVIC_ST_CTRL_INTEN 0x00000002 ///< Interrupt enable
00114 #define NVIC_ST_CTRL_ENABLE 0x00000001 ///< Counter mode
00115
00116
00120
00121 #define NVIC_ST_RELOAD_M 0x00FFFFFF ///< Counter load value
00122 #define NVIC_ST_RELOAD_S 0
00123
00124
00129
00130 #define NVIC_ST_CURRENT_M 0x00FFFFFF ///< Counter current value
00131 #define NVIC_ST_CURRENT_S 0
00132
00133
00137
00138 #define NVIC_ST_CAL_NOREF 0x80000000 ///< No reference clock
00139 #define NVIC_ST_CAL_SKEW 0x40000000 ///< Clock skew
00140 #define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF ///< 1ms reference value
00141 #define NVIC_ST_CAL_ONEMS_S 0
00142
00143
00147
00148 #define NVIC_EN0_INT31 0x80000000 ///< Interrupt 31 enable
00149 #define NVIC_EN0_INT30 0x40000000 ///< Interrupt 30 enable
00150 #define NVIC_EN0_INT29 0x20000000 ///< Interrupt 29 enable
00151 #define NVIC_EN0_INT28 0x10000000 ///< Interrupt 28 enable
00152 #define NVIC_EN0_INT27 0x08000000 ///< Interrupt 27 enable
00153 #define NVIC_EN0_INT26 0x04000000 ///< Interrupt 26 enable
00154 #define NVIC_EN0_INT25 0x02000000 ///< Interrupt 25 enable
00155 #define NVIC_EN0_INT24 0x01000000 ///< Interrupt 24 enable
00156 #define NVIC_EN0_INT23 0x00800000 ///< Interrupt 23 enable
00157 #define NVIC_EN0_INT22 0x00400000 ///< Interrupt 22 enable
00158 #define NVIC_EN0_INT21 0x00200000 ///< Interrupt 21 enable
00159 #define NVIC_EN0_INT20 0x00100000 ///< Interrupt 20 enable
00160 #define NVIC_EN0_INT19 0x00080000 ///< Interrupt 19 enable
00161 #define NVIC_EN0_INT18 0x00040000 ///< Interrupt 18 enable
00162 #define NVIC_EN0_INT17 0x00020000 ///< Interrupt 17 enable
00163 #define NVIC_EN0_INT16 0x00010000 ///< Interrupt 16 enable
00164 #define NVIC_EN0_INT15 0x00008000 ///< Interrupt 15 enable
00165 #define NVIC_EN0_INT14 0x00004000 ///< Interrupt 14 enable
00166 #define NVIC_EN0_INT13 0x00002000 ///< Interrupt 13 enable
00167 #define NVIC_EN0_INT12 0x00001000 ///< Interrupt 12 enable
00168 #define NVIC_EN0_INT11 0x00000800 ///< Interrupt 11 enable
00169 #define NVIC_EN0_INT10 0x00000400 ///< Interrupt 10 enable
00170 #define NVIC_EN0_INT9 0x00000200 ///< Interrupt 9 enable
00171 #define NVIC_EN0_INT8 0x00000100 ///< Interrupt 8 enable
00172 #define NVIC_EN0_INT7 0x00000080 ///< Interrupt 7 enable
00173 #define NVIC_EN0_INT6 0x00000040 ///< Interrupt 6 enable
00174 #define NVIC_EN0_INT5 0x00000020 ///< Interrupt 5 enable
00175 #define NVIC_EN0_INT4 0x00000010 ///< Interrupt 4 enable
00176 #define NVIC_EN0_INT3 0x00000008 ///< Interrupt 3 enable
00177 #define NVIC_EN0_INT2 0x00000004 ///< Interrupt 2 enable
00178 #define NVIC_EN0_INT1 0x00000002 ///< Interrupt 1 enable
00179 #define NVIC_EN0_INT0 0x00000001 ///< Interrupt 0 enable
00180
00181
00185
00186 #define NVIC_EN1_INT59 0x08000000 ///< Interrupt 59 enable
00187 #define NVIC_EN1_INT58 0x04000000 ///< Interrupt 58 enable
00188 #define NVIC_EN1_INT57 0x02000000 ///< Interrupt 57 enable
00189 #define NVIC_EN1_INT56 0x01000000 ///< Interrupt 56 enable
00190 #define NVIC_EN1_INT55 0x00800000 ///< Interrupt 55 enable
00191 #define NVIC_EN1_INT54 0x00400000 ///< Interrupt 54 enable
00192 #define NVIC_EN1_INT53 0x00200000 ///< Interrupt 53 enable
00193 #define NVIC_EN1_INT52 0x00100000 ///< Interrupt 52 enable
00194 #define NVIC_EN1_INT51 0x00080000 ///< Interrupt 51 enable
00195 #define NVIC_EN1_INT50 0x00040000 ///< Interrupt 50 enable
00196 #define NVIC_EN1_INT49 0x00020000 ///< Interrupt 49 enable
00197 #define NVIC_EN1_INT48 0x00010000 ///< Interrupt 48 enable
00198 #define NVIC_EN1_INT47 0x00008000 ///< Interrupt 47 enable
00199 #define NVIC_EN1_INT46 0x00004000 ///< Interrupt 46 enable
00200 #define NVIC_EN1_INT45 0x00002000 ///< Interrupt 45 enable
00201 #define NVIC_EN1_INT44 0x00001000 ///< Interrupt 44 enable
00202 #define NVIC_EN1_INT43 0x00000800 ///< Interrupt 43 enable
00203 #define NVIC_EN1_INT42 0x00000400 ///< Interrupt 42 enable
00204 #define NVIC_EN1_INT41 0x00000200 ///< Interrupt 41 enable
00205 #define NVIC_EN1_INT40 0x00000100 ///< Interrupt 40 enable
00206 #define NVIC_EN1_INT39 0x00000080 ///< Interrupt 39 enable
00207 #define NVIC_EN1_INT38 0x00000040 ///< Interrupt 38 enable
00208 #define NVIC_EN1_INT37 0x00000020 ///< Interrupt 37 enable
00209 #define NVIC_EN1_INT36 0x00000010 ///< Interrupt 36 enable
00210 #define NVIC_EN1_INT35 0x00000008 ///< Interrupt 35 enable
00211 #define NVIC_EN1_INT34 0x00000004 ///< Interrupt 34 enable
00212 #define NVIC_EN1_INT33 0x00000002 ///< Interrupt 33 enable
00213 #define NVIC_EN1_INT32 0x00000001 ///< Interrupt 32 enable
00214
00215
00219
00220 #define NVIC_DIS0_INT31 0x80000000 ///< Interrupt 31 disable
00221 #define NVIC_DIS0_INT30 0x40000000 ///< Interrupt 30 disable
00222 #define NVIC_DIS0_INT29 0x20000000 ///< Interrupt 29 disable
00223 #define NVIC_DIS0_INT28 0x10000000 ///< Interrupt 28 disable
00224 #define NVIC_DIS0_INT27 0x08000000 ///< Interrupt 27 disable
00225 #define NVIC_DIS0_INT26 0x04000000 ///< Interrupt 26 disable
00226 #define NVIC_DIS0_INT25 0x02000000 ///< Interrupt 25 disable
00227 #define NVIC_DIS0_INT24 0x01000000 ///< Interrupt 24 disable
00228 #define NVIC_DIS0_INT23 0x00800000 ///< Interrupt 23 disable
00229 #define NVIC_DIS0_INT22 0x00400000 ///< Interrupt 22 disable
00230 #define NVIC_DIS0_INT21 0x00200000 ///< Interrupt 21 disable
00231 #define NVIC_DIS0_INT20 0x00100000 ///< Interrupt 20 disable
00232 #define NVIC_DIS0_INT19 0x00080000 ///< Interrupt 19 disable
00233 #define NVIC_DIS0_INT18 0x00040000 ///< Interrupt 18 disable
00234 #define NVIC_DIS0_INT17 0x00020000 ///< Interrupt 17 disable
00235 #define NVIC_DIS0_INT16 0x00010000 ///< Interrupt 16 disable
00236 #define NVIC_DIS0_INT15 0x00008000 ///< Interrupt 15 disable
00237 #define NVIC_DIS0_INT14 0x00004000 ///< Interrupt 14 disable
00238 #define NVIC_DIS0_INT13 0x00002000 ///< Interrupt 13 disable
00239 #define NVIC_DIS0_INT12 0x00001000 ///< Interrupt 12 disable
00240 #define NVIC_DIS0_INT11 0x00000800 ///< Interrupt 11 disable
00241 #define NVIC_DIS0_INT10 0x00000400 ///< Interrupt 10 disable
00242 #define NVIC_DIS0_INT9 0x00000200 ///< Interrupt 9 disable
00243 #define NVIC_DIS0_INT8 0x00000100 ///< Interrupt 8 disable
00244 #define NVIC_DIS0_INT7 0x00000080 ///< Interrupt 7 disable
00245 #define NVIC_DIS0_INT6 0x00000040 ///< Interrupt 6 disable
00246 #define NVIC_DIS0_INT5 0x00000020 ///< Interrupt 5 disable
00247 #define NVIC_DIS0_INT4 0x00000010 ///< Interrupt 4 disable
00248 #define NVIC_DIS0_INT3 0x00000008 ///< Interrupt 3 disable
00249 #define NVIC_DIS0_INT2 0x00000004 ///< Interrupt 2 disable
00250 #define NVIC_DIS0_INT1 0x00000002 ///< Interrupt 1 disable
00251 #define NVIC_DIS0_INT0 0x00000001 ///< Interrupt 0 disable
00252
00253
00257
00258 #define NVIC_DIS1_INT59 0x08000000 ///< Interrupt 59 disable
00259 #define NVIC_DIS1_INT58 0x04000000 ///< Interrupt 58 disable
00260 #define NVIC_DIS1_INT57 0x02000000 ///< Interrupt 57 disable
00261 #define NVIC_DIS1_INT56 0x01000000 ///< Interrupt 56 disable
00262 #define NVIC_DIS1_INT55 0x00800000 ///< Interrupt 55 disable
00263 #define NVIC_DIS1_INT54 0x00400000 ///< Interrupt 54 disable
00264 #define NVIC_DIS1_INT53 0x00200000 ///< Interrupt 53 disable
00265 #define NVIC_DIS1_INT52 0x00100000 ///< Interrupt 52 disable
00266 #define NVIC_DIS1_INT51 0x00080000 ///< Interrupt 51 disable
00267 #define NVIC_DIS1_INT50 0x00040000 ///< Interrupt 50 disable
00268 #define NVIC_DIS1_INT49 0x00020000 ///< Interrupt 49 disable
00269 #define NVIC_DIS1_INT48 0x00010000 ///< Interrupt 48 disable
00270 #define NVIC_DIS1_INT47 0x00008000 ///< Interrupt 47 disable
00271 #define NVIC_DIS1_INT46 0x00004000 ///< Interrupt 46 disable
00272 #define NVIC_DIS1_INT45 0x00002000 ///< Interrupt 45 disable
00273 #define NVIC_DIS1_INT44 0x00001000 ///< Interrupt 44 disable
00274 #define NVIC_DIS1_INT43 0x00000800 ///< Interrupt 43 disable
00275 #define NVIC_DIS1_INT42 0x00000400 ///< Interrupt 42 disable
00276 #define NVIC_DIS1_INT41 0x00000200 ///< Interrupt 41 disable
00277 #define NVIC_DIS1_INT40 0x00000100 ///< Interrupt 40 disable
00278 #define NVIC_DIS1_INT39 0x00000080 ///< Interrupt 39 disable
00279 #define NVIC_DIS1_INT38 0x00000040 ///< Interrupt 38 disable
00280 #define NVIC_DIS1_INT37 0x00000020 ///< Interrupt 37 disable
00281 #define NVIC_DIS1_INT36 0x00000010 ///< Interrupt 36 disable
00282 #define NVIC_DIS1_INT35 0x00000008 ///< Interrupt 35 disable
00283 #define NVIC_DIS1_INT34 0x00000004 ///< Interrupt 34 disable
00284 #define NVIC_DIS1_INT33 0x00000002 ///< Interrupt 33 disable
00285 #define NVIC_DIS1_INT32 0x00000001 ///< Interrupt 32 disable
00286
00287
00291
00292 #define NVIC_PEND0_INT31 0x80000000 ///< Interrupt 31 pend
00293 #define NVIC_PEND0_INT30 0x40000000 ///< Interrupt 30 pend
00294 #define NVIC_PEND0_INT29 0x20000000 ///< Interrupt 29 pend
00295 #define NVIC_PEND0_INT28 0x10000000 ///< Interrupt 28 pend
00296 #define NVIC_PEND0_INT27 0x08000000 ///< Interrupt 27 pend
00297 #define NVIC_PEND0_INT26 0x04000000 ///< Interrupt 26 pend
00298 #define NVIC_PEND0_INT25 0x02000000 ///< Interrupt 25 pend
00299 #define NVIC_PEND0_INT24 0x01000000 ///< Interrupt 24 pend
00300 #define NVIC_PEND0_INT23 0x00800000 ///< Interrupt 23 pend
00301 #define NVIC_PEND0_INT22 0x00400000 ///< Interrupt 22 pend
00302 #define NVIC_PEND0_INT21 0x00200000 ///< Interrupt 21 pend
00303 #define NVIC_PEND0_INT20 0x00100000 ///< Interrupt 20 pend
00304 #define NVIC_PEND0_INT19 0x00080000 ///< Interrupt 19 pend
00305 #define NVIC_PEND0_INT18 0x00040000 ///< Interrupt 18 pend
00306 #define NVIC_PEND0_INT17 0x00020000 ///< Interrupt 17 pend
00307 #define NVIC_PEND0_INT16 0x00010000 ///< Interrupt 16 pend
00308 #define NVIC_PEND0_INT15 0x00008000 ///< Interrupt 15 pend
00309 #define NVIC_PEND0_INT14 0x00004000 ///< Interrupt 14 pend
00310 #define NVIC_PEND0_INT13 0x00002000 ///< Interrupt 13 pend
00311 #define NVIC_PEND0_INT12 0x00001000 ///< Interrupt 12 pend
00312 #define NVIC_PEND0_INT11 0x00000800 ///< Interrupt 11 pend
00313 #define NVIC_PEND0_INT10 0x00000400 ///< Interrupt 10 pend
00314 #define NVIC_PEND0_INT9 0x00000200 ///< Interrupt 9 pend
00315 #define NVIC_PEND0_INT8 0x00000100 ///< Interrupt 8 pend
00316 #define NVIC_PEND0_INT7 0x00000080 ///< Interrupt 7 pend
00317 #define NVIC_PEND0_INT6 0x00000040 ///< Interrupt 6 pend
00318 #define NVIC_PEND0_INT5 0x00000020 ///< Interrupt 5 pend
00319 #define NVIC_PEND0_INT4 0x00000010 ///< Interrupt 4 pend
00320 #define NVIC_PEND0_INT3 0x00000008 ///< Interrupt 3 pend
00321 #define NVIC_PEND0_INT2 0x00000004 ///< Interrupt 2 pend
00322 #define NVIC_PEND0_INT1 0x00000002 ///< Interrupt 1 pend
00323 #define NVIC_PEND0_INT0 0x00000001 ///< Interrupt 0 pend
00324
00325
00329
00330 #define NVIC_PEND1_INT59 0x08000000 ///< Interrupt 59 pend
00331 #define NVIC_PEND1_INT58 0x04000000 ///< Interrupt 58 pend
00332 #define NVIC_PEND1_INT57 0x02000000 ///< Interrupt 57 pend
00333 #define NVIC_PEND1_INT56 0x01000000 ///< Interrupt 56 pend
00334 #define NVIC_PEND1_INT55 0x00800000 ///< Interrupt 55 pend
00335 #define NVIC_PEND1_INT54 0x00400000 ///< Interrupt 54 pend
00336 #define NVIC_PEND1_INT53 0x00200000 ///< Interrupt 53 pend
00337 #define NVIC_PEND1_INT52 0x00100000 ///< Interrupt 52 pend
00338 #define NVIC_PEND1_INT51 0x00080000 ///< Interrupt 51 pend
00339 #define NVIC_PEND1_INT50 0x00040000 ///< Interrupt 50 pend
00340 #define NVIC_PEND1_INT49 0x00020000 ///< Interrupt 49 pend
00341 #define NVIC_PEND1_INT48 0x00010000 ///< Interrupt 48 pend
00342 #define NVIC_PEND1_INT47 0x00008000 ///< Interrupt 47 pend
00343 #define NVIC_PEND1_INT46 0x00004000 ///< Interrupt 46 pend
00344 #define NVIC_PEND1_INT45 0x00002000 ///< Interrupt 45 pend
00345 #define NVIC_PEND1_INT44 0x00001000 ///< Interrupt 44 pend
00346 #define NVIC_PEND1_INT43 0x00000800 ///< Interrupt 43 pend
00347 #define NVIC_PEND1_INT42 0x00000400 ///< Interrupt 42 pend
00348 #define NVIC_PEND1_INT41 0x00000200 ///< Interrupt 41 pend
00349 #define NVIC_PEND1_INT40 0x00000100 ///< Interrupt 40 pend
00350 #define NVIC_PEND1_INT39 0x00000080 ///< Interrupt 39 pend
00351 #define NVIC_PEND1_INT38 0x00000040 ///< Interrupt 38 pend
00352 #define NVIC_PEND1_INT37 0x00000020 ///< Interrupt 37 pend
00353 #define NVIC_PEND1_INT36 0x00000010 ///< Interrupt 36 pend
00354 #define NVIC_PEND1_INT35 0x00000008 ///< Interrupt 35 pend
00355 #define NVIC_PEND1_INT34 0x00000004 ///< Interrupt 34 pend
00356 #define NVIC_PEND1_INT33 0x00000002 ///< Interrupt 33 pend
00357 #define NVIC_PEND1_INT32 0x00000001 ///< Interrupt 32 pend
00358
00359
00363
00364 #define NVIC_UNPEND0_INT31 0x80000000 ///< Interrupt 31 unpend
00365 #define NVIC_UNPEND0_INT30 0x40000000 ///< Interrupt 30 unpend
00366 #define NVIC_UNPEND0_INT29 0x20000000 ///< Interrupt 29 unpend
00367 #define NVIC_UNPEND0_INT28 0x10000000 ///< Interrupt 28 unpend
00368 #define NVIC_UNPEND0_INT27 0x08000000 ///< Interrupt 27 unpend
00369 #define NVIC_UNPEND0_INT26 0x04000000 ///< Interrupt 26 unpend
00370 #define NVIC_UNPEND0_INT25 0x02000000 ///< Interrupt 25 unpend
00371 #define NVIC_UNPEND0_INT24 0x01000000 ///< Interrupt 24 unpend
00372 #define NVIC_UNPEND0_INT23 0x00800000 ///< Interrupt 23 unpend
00373 #define NVIC_UNPEND0_INT22 0x00400000 ///< Interrupt 22 unpend
00374 #define NVIC_UNPEND0_INT21 0x00200000 ///< Interrupt 21 unpend
00375 #define NVIC_UNPEND0_INT20 0x00100000 ///< Interrupt 20 unpend
00376 #define NVIC_UNPEND0_INT19 0x00080000 ///< Interrupt 19 unpend
00377 #define NVIC_UNPEND0_INT18 0x00040000 ///< Interrupt 18 unpend
00378 #define NVIC_UNPEND0_INT17 0x00020000 ///< Interrupt 17 unpend
00379 #define NVIC_UNPEND0_INT16 0x00010000 ///< Interrupt 16 unpend
00380 #define NVIC_UNPEND0_INT15 0x00008000 ///< Interrupt 15 unpend
00381 #define NVIC_UNPEND0_INT14 0x00004000 ///< Interrupt 14 unpend
00382 #define NVIC_UNPEND0_INT13 0x00002000 ///< Interrupt 13 unpend
00383 #define NVIC_UNPEND0_INT12 0x00001000 ///< Interrupt 12 unpend
00384 #define NVIC_UNPEND0_INT11 0x00000800 ///< Interrupt 11 unpend
00385 #define NVIC_UNPEND0_INT10 0x00000400 ///< Interrupt 10 unpend
00386 #define NVIC_UNPEND0_INT9 0x00000200 ///< Interrupt 9 unpend
00387 #define NVIC_UNPEND0_INT8 0x00000100 ///< Interrupt 8 unpend
00388 #define NVIC_UNPEND0_INT7 0x00000080 ///< Interrupt 7 unpend
00389 #define NVIC_UNPEND0_INT6 0x00000040 ///< Interrupt 6 unpend
00390 #define NVIC_UNPEND0_INT5 0x00000020 ///< Interrupt 5 unpend
00391 #define NVIC_UNPEND0_INT4 0x00000010 ///< Interrupt 4 unpend
00392 #define NVIC_UNPEND0_INT3 0x00000008 ///< Interrupt 3 unpend
00393 #define NVIC_UNPEND0_INT2 0x00000004 ///< Interrupt 2 unpend
00394 #define NVIC_UNPEND0_INT1 0x00000002 ///< Interrupt 1 unpend
00395 #define NVIC_UNPEND0_INT0 0x00000001 ///< Interrupt 0 unpend
00396
00397
00401
00402 #define NVIC_UNPEND1_INT59 0x08000000 ///< Interrupt 59 unpend
00403 #define NVIC_UNPEND1_INT58 0x04000000 ///< Interrupt 58 unpend
00404 #define NVIC_UNPEND1_INT57 0x02000000 ///< Interrupt 57 unpend
00405 #define NVIC_UNPEND1_INT56 0x01000000 ///< Interrupt 56 unpend
00406 #define NVIC_UNPEND1_INT55 0x00800000 ///< Interrupt 55 unpend
00407 #define NVIC_UNPEND1_INT54 0x00400000 ///< Interrupt 54 unpend
00408 #define NVIC_UNPEND1_INT53 0x00200000 ///< Interrupt 53 unpend
00409 #define NVIC_UNPEND1_INT52 0x00100000 ///< Interrupt 52 unpend
00410 #define NVIC_UNPEND1_INT51 0x00080000 ///< Interrupt 51 unpend
00411 #define NVIC_UNPEND1_INT50 0x00040000 ///< Interrupt 50 unpend
00412 #define NVIC_UNPEND1_INT49 0x00020000 ///< Interrupt 49 unpend
00413 #define NVIC_UNPEND1_INT48 0x00010000 ///< Interrupt 48 unpend
00414 #define NVIC_UNPEND1_INT47 0x00008000 ///< Interrupt 47 unpend
00415 #define NVIC_UNPEND1_INT46 0x00004000 ///< Interrupt 46 unpend
00416 #define NVIC_UNPEND1_INT45 0x00002000 ///< Interrupt 45 unpend
00417 #define NVIC_UNPEND1_INT44 0x00001000 ///< Interrupt 44 unpend
00418 #define NVIC_UNPEND1_INT43 0x00000800 ///< Interrupt 43 unpend
00419 #define NVIC_UNPEND1_INT42 0x00000400 ///< Interrupt 42 unpend
00420 #define NVIC_UNPEND1_INT41 0x00000200 ///< Interrupt 41 unpend
00421 #define NVIC_UNPEND1_INT40 0x00000100 ///< Interrupt 40 unpend
00422 #define NVIC_UNPEND1_INT39 0x00000080 ///< Interrupt 39 unpend
00423 #define NVIC_UNPEND1_INT38 0x00000040 ///< Interrupt 38 unpend
00424 #define NVIC_UNPEND1_INT37 0x00000020 ///< Interrupt 37 unpend
00425 #define NVIC_UNPEND1_INT36 0x00000010 ///< Interrupt 36 unpend
00426 #define NVIC_UNPEND1_INT35 0x00000008 ///< Interrupt 35 unpend
00427 #define NVIC_UNPEND1_INT34 0x00000004 ///< Interrupt 34 unpend
00428 #define NVIC_UNPEND1_INT33 0x00000002 ///< Interrupt 33 unpend
00429 #define NVIC_UNPEND1_INT32 0x00000001 ///< Interrupt 32 unpend
00430
00431
00435
00436 #define NVIC_ACTIVE0_INT31 0x80000000 ///< Interrupt 31 active
00437 #define NVIC_ACTIVE0_INT30 0x40000000 ///< Interrupt 30 active
00438 #define NVIC_ACTIVE0_INT29 0x20000000 ///< Interrupt 29 active
00439 #define NVIC_ACTIVE0_INT28 0x10000000 ///< Interrupt 28 active
00440 #define NVIC_ACTIVE0_INT27 0x08000000 ///< Interrupt 27 active
00441 #define NVIC_ACTIVE0_INT26 0x04000000 ///< Interrupt 26 active
00442 #define NVIC_ACTIVE0_INT25 0x02000000 ///< Interrupt 25 active
00443 #define NVIC_ACTIVE0_INT24 0x01000000 ///< Interrupt 24 active
00444 #define NVIC_ACTIVE0_INT23 0x00800000 ///< Interrupt 23 active
00445 #define NVIC_ACTIVE0_INT22 0x00400000 ///< Interrupt 22 active
00446 #define NVIC_ACTIVE0_INT21 0x00200000 ///< Interrupt 21 active
00447 #define NVIC_ACTIVE0_INT20 0x00100000 ///< Interrupt 20 active
00448 #define NVIC_ACTIVE0_INT19 0x00080000 ///< Interrupt 19 active
00449 #define NVIC_ACTIVE0_INT18 0x00040000 ///< Interrupt 18 active
00450 #define NVIC_ACTIVE0_INT17 0x00020000 ///< Interrupt 17 active
00451 #define NVIC_ACTIVE0_INT16 0x00010000 ///< Interrupt 16 active
00452 #define NVIC_ACTIVE0_INT15 0x00008000 ///< Interrupt 15 active
00453 #define NVIC_ACTIVE0_INT14 0x00004000 ///< Interrupt 14 active
00454 #define NVIC_ACTIVE0_INT13 0x00002000 ///< Interrupt 13 active
00455 #define NVIC_ACTIVE0_INT12 0x00001000 ///< Interrupt 12 active
00456 #define NVIC_ACTIVE0_INT11 0x00000800 ///< Interrupt 11 active
00457 #define NVIC_ACTIVE0_INT10 0x00000400 ///< Interrupt 10 active
00458 #define NVIC_ACTIVE0_INT9 0x00000200 ///< Interrupt 9 active
00459 #define NVIC_ACTIVE0_INT8 0x00000100 ///< Interrupt 8 active
00460 #define NVIC_ACTIVE0_INT7 0x00000080 ///< Interrupt 7 active
00461 #define NVIC_ACTIVE0_INT6 0x00000040 ///< Interrupt 6 active
00462 #define NVIC_ACTIVE0_INT5 0x00000020 ///< Interrupt 5 active
00463 #define NVIC_ACTIVE0_INT4 0x00000010 ///< Interrupt 4 active
00464 #define NVIC_ACTIVE0_INT3 0x00000008 ///< Interrupt 3 active
00465 #define NVIC_ACTIVE0_INT2 0x00000004 ///< Interrupt 2 active
00466 #define NVIC_ACTIVE0_INT1 0x00000002 ///< Interrupt 1 active
00467 #define NVIC_ACTIVE0_INT0 0x00000001 ///< Interrupt 0 active
00468
00469
00473
00474 #define NVIC_ACTIVE1_INT59 0x08000000 ///< Interrupt 59 active
00475 #define NVIC_ACTIVE1_INT58 0x04000000 ///< Interrupt 58 active
00476 #define NVIC_ACTIVE1_INT57 0x02000000 ///< Interrupt 57 active
00477 #define NVIC_ACTIVE1_INT56 0x01000000 ///< Interrupt 56 active
00478 #define NVIC_ACTIVE1_INT55 0x00800000 ///< Interrupt 55 active
00479 #define NVIC_ACTIVE1_INT54 0x00400000 ///< Interrupt 54 active
00480 #define NVIC_ACTIVE1_INT53 0x00200000 ///< Interrupt 53 active
00481 #define NVIC_ACTIVE1_INT52 0x00100000 ///< Interrupt 52 active
00482 #define NVIC_ACTIVE1_INT51 0x00080000 ///< Interrupt 51 active
00483 #define NVIC_ACTIVE1_INT50 0x00040000 ///< Interrupt 50 active
00484 #define NVIC_ACTIVE1_INT49 0x00020000 ///< Interrupt 49 active
00485 #define NVIC_ACTIVE1_INT48 0x00010000 ///< Interrupt 48 active
00486 #define NVIC_ACTIVE1_INT47 0x00008000 ///< Interrupt 47 active
00487 #define NVIC_ACTIVE1_INT46 0x00004000 ///< Interrupt 46 active
00488 #define NVIC_ACTIVE1_INT45 0x00002000 ///< Interrupt 45 active
00489 #define NVIC_ACTIVE1_INT44 0x00001000 ///< Interrupt 44 active
00490 #define NVIC_ACTIVE1_INT43 0x00000800 ///< Interrupt 43 active
00491 #define NVIC_ACTIVE1_INT42 0x00000400 ///< Interrupt 42 active
00492 #define NVIC_ACTIVE1_INT41 0x00000200 ///< Interrupt 41 active
00493 #define NVIC_ACTIVE1_INT40 0x00000100 ///< Interrupt 40 active
00494 #define NVIC_ACTIVE1_INT39 0x00000080 ///< Interrupt 39 active
00495 #define NVIC_ACTIVE1_INT38 0x00000040 ///< Interrupt 38 active
00496 #define NVIC_ACTIVE1_INT37 0x00000020 ///< Interrupt 37 active
00497 #define NVIC_ACTIVE1_INT36 0x00000010 ///< Interrupt 36 active
00498 #define NVIC_ACTIVE1_INT35 0x00000008 ///< Interrupt 35 active
00499 #define NVIC_ACTIVE1_INT34 0x00000004 ///< Interrupt 34 active
00500 #define NVIC_ACTIVE1_INT33 0x00000002 ///< Interrupt 33 active
00501 #define NVIC_ACTIVE1_INT32 0x00000001 ///< Interrupt 32 active
00502
00503
00507
00508 #define NVIC_PRI0_INT3_M 0xFF000000 ///< Interrupt 3 priority mask
00509 #define NVIC_PRI0_INT2_M 0x00FF0000 ///< Interrupt 2 priority mask
00510 #define NVIC_PRI0_INT1_M 0x0000FF00 ///< Interrupt 1 priority mask
00511 #define NVIC_PRI0_INT0_M 0x000000FF ///< Interrupt 0 priority mask
00512 #define NVIC_PRI0_INT3_S 24
00513 #define NVIC_PRI0_INT2_S 16
00514 #define NVIC_PRI0_INT1_S 8
00515 #define NVIC_PRI0_INT0_S 0
00516
00517
00521
00522 #define NVIC_PRI1_INT7_M 0xFF000000 ///< Interrupt 7 priority mask
00523 #define NVIC_PRI1_INT6_M 0x00FF0000 ///< Interrupt 6 priority mask
00524 #define NVIC_PRI1_INT5_M 0x0000FF00 ///< Interrupt 5 priority mask
00525 #define NVIC_PRI1_INT4_M 0x000000FF ///< Interrupt 4 priority mask
00526 #define NVIC_PRI1_INT7_S 24
00527 #define NVIC_PRI1_INT6_S 16
00528 #define NVIC_PRI1_INT5_S 8
00529 #define NVIC_PRI1_INT4_S 0
00530
00531
00535
00536 #define NVIC_PRI2_INT11_M 0xFF000000 ///< Interrupt 11 priority mask
00537 #define NVIC_PRI2_INT10_M 0x00FF0000 ///< Interrupt 10 priority mask
00538 #define NVIC_PRI2_INT9_M 0x0000FF00 ///< Interrupt 9 priority mask
00539 #define NVIC_PRI2_INT8_M 0x000000FF ///< Interrupt 8 priority mask
00540 #define NVIC_PRI2_INT11_S 24
00541 #define NVIC_PRI2_INT10_S 16
00542 #define NVIC_PRI2_INT9_S 8
00543 #define NVIC_PRI2_INT8_S 0
00544
00545
00549
00550 #define NVIC_PRI3_INT15_M 0xFF000000 ///< Interrupt 15 priority mask
00551 #define NVIC_PRI3_INT14_M 0x00FF0000 ///< Interrupt 14 priority mask
00552 #define NVIC_PRI3_INT13_M 0x0000FF00 ///< Interrupt 13 priority mask
00553 #define NVIC_PRI3_INT12_M 0x000000FF ///< Interrupt 12 priority mask
00554 #define NVIC_PRI3_INT15_S 24
00555 #define NVIC_PRI3_INT14_S 16
00556 #define NVIC_PRI3_INT13_S 8
00557 #define NVIC_PRI3_INT12_S 0
00558
00559
00563
00564 #define NVIC_PRI4_INT19_M 0xFF000000 ///< Interrupt 19 priority mask
00565 #define NVIC_PRI4_INT18_M 0x00FF0000 ///< Interrupt 18 priority mask
00566 #define NVIC_PRI4_INT17_M 0x0000FF00 ///< Interrupt 17 priority mask
00567 #define NVIC_PRI4_INT16_M 0x000000FF ///< Interrupt 16 priority mask
00568 #define NVIC_PRI4_INT19_S 24
00569 #define NVIC_PRI4_INT18_S 16
00570 #define NVIC_PRI4_INT17_S 8
00571 #define NVIC_PRI4_INT16_S 0
00572
00573
00577
00578 #define NVIC_PRI5_INT23_M 0xFF000000 ///< Interrupt 23 priority mask
00579 #define NVIC_PRI5_INT22_M 0x00FF0000 ///< Interrupt 22 priority mask
00580 #define NVIC_PRI5_INT21_M 0x0000FF00 ///< Interrupt 21 priority mask
00581 #define NVIC_PRI5_INT20_M 0x000000FF ///< Interrupt 20 priority mask
00582 #define NVIC_PRI5_INT23_S 24
00583 #define NVIC_PRI5_INT22_S 16
00584 #define NVIC_PRI5_INT21_S 8
00585 #define NVIC_PRI5_INT20_S 0
00586
00587
00591
00592 #define NVIC_PRI6_INT27_M 0xFF000000 ///< Interrupt 27 priority mask
00593 #define NVIC_PRI6_INT26_M 0x00FF0000 ///< Interrupt 26 priority mask
00594 #define NVIC_PRI6_INT25_M 0x0000FF00 ///< Interrupt 25 priority mask
00595 #define NVIC_PRI6_INT24_M 0x000000FF ///< Interrupt 24 priority mask
00596 #define NVIC_PRI6_INT27_S 24
00597 #define NVIC_PRI6_INT26_S 16
00598 #define NVIC_PRI6_INT25_S 8
00599 #define NVIC_PRI6_INT24_S 0
00600
00601
00605
00606 #define NVIC_PRI7_INT31_M 0xFF000000 ///< Interrupt 31 priority mask
00607 #define NVIC_PRI7_INT30_M 0x00FF0000 ///< Interrupt 30 priority mask
00608 #define NVIC_PRI7_INT29_M 0x0000FF00 ///< Interrupt 29 priority mask
00609 #define NVIC_PRI7_INT28_M 0x000000FF ///< Interrupt 28 priority mask
00610 #define NVIC_PRI7_INT31_S 24
00611 #define NVIC_PRI7_INT30_S 16
00612 #define NVIC_PRI7_INT29_S 8
00613 #define NVIC_PRI7_INT28_S 0
00614
00615
00619
00620 #define NVIC_PRI8_INT35_M 0xFF000000 ///< Interrupt 35 priority mask
00621 #define NVIC_PRI8_INT34_M 0x00FF0000 ///< Interrupt 34 priority mask
00622 #define NVIC_PRI8_INT33_M 0x0000FF00 ///< Interrupt 33 priority mask
00623 #define NVIC_PRI8_INT32_M 0x000000FF ///< Interrupt 32 priority mask
00624 #define NVIC_PRI8_INT35_S 24
00625 #define NVIC_PRI8_INT34_S 16
00626 #define NVIC_PRI8_INT33_S 8
00627 #define NVIC_PRI8_INT32_S 0
00628
00629
00633
00634 #define NVIC_PRI9_INT39_M 0xFF000000 ///< Interrupt 39 priority mask
00635 #define NVIC_PRI9_INT38_M 0x00FF0000 ///< Interrupt 38 priority mask
00636 #define NVIC_PRI9_INT37_M 0x0000FF00 ///< Interrupt 37 priority mask
00637 #define NVIC_PRI9_INT36_M 0x000000FF ///< Interrupt 36 priority mask
00638 #define NVIC_PRI9_INT39_S 24
00639 #define NVIC_PRI9_INT38_S 16
00640 #define NVIC_PRI9_INT37_S 8
00641 #define NVIC_PRI9_INT36_S 0
00642
00643
00647
00648 #define NVIC_PRI10_INT43_M 0xFF000000 ///< Interrupt 43 priority mask
00649 #define NVIC_PRI10_INT42_M 0x00FF0000 ///< Interrupt 42 priority mask
00650 #define NVIC_PRI10_INT41_M 0x0000FF00 ///< Interrupt 41 priority mask
00651 #define NVIC_PRI10_INT40_M 0x000000FF ///< Interrupt 40 priority mask
00652 #define NVIC_PRI10_INT43_S 24
00653 #define NVIC_PRI10_INT42_S 16
00654 #define NVIC_PRI10_INT41_S 8
00655 #define NVIC_PRI10_INT40_S 0
00656
00657
00661
00662 #define NVIC_CPUID_IMP_M 0xFF000000 ///< Implementer
00663 #define NVIC_CPUID_VAR_M 0x00F00000 ///< Variant
00664 #define NVIC_CPUID_PARTNO_M 0x0000FFF0 ///< Processor part number
00665 #define NVIC_CPUID_REV_M 0x0000000F ///< Revision
00666
00667
00671
00672 #define NVIC_INT_CTRL_NMI_SET 0x80000000 ///< Pend a NMI
00673 #define NVIC_INT_CTRL_PEND_SV 0x10000000 ///< Pend a PendSV
00674 #define NVIC_INT_CTRL_UNPEND_SV 0x08000000 ///< Unpend a PendSV
00675 #define NVIC_INT_CTRL_PENDSTSET 0x04000000 ///< Set pending SysTick interrupt
00676 #define NVIC_INT_CTRL_PENDSTCLR 0x02000000 ///< Clear pending SysTick interrupt
00677 #define NVIC_INT_CTRL_ISR_PRE 0x00800000 ///< Debug interrupt handling
00678 #define NVIC_INT_CTRL_ISR_PEND 0x00400000 ///< Debug interrupt pending
00679 #define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 ///< Highest pending exception
00680 #define NVIC_INT_CTRL_RET_BASE 0x00000800 ///< Return to base
00681 #define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF ///< Current active exception
00682 #define NVIC_INT_CTRL_VEC_PEN_S 12
00683 #define NVIC_INT_CTRL_VEC_ACT_S 0
00684
00685
00689
00690 #define NVIC_VTABLE_BASE 0x20000000 ///< Vector table base
00691 #define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 ///< Vector table offset
00692 #define NVIC_VTABLE_OFFSET_S 8
00693
00694
00698
00699 #define NVIC_APINT_VECTKEY_M 0xFFFF0000 ///< Vector key mask
00700 #define NVIC_APINT_VECTKEY 0x05FA0000 ///< Vector key
00701 #define NVIC_APINT_ENDIANESS 0x00008000 ///< Data endianess
00702 #define NVIC_APINT_PRIGROUP_M 0x00000700 ///< Priority group
00703 #define NVIC_APINT_PRIGROUP_0_8 0x00000700 ///< Priority group 0.8 split
00704 #define NVIC_APINT_PRIGROUP_1_7 0x00000600 ///< Priority group 1.7 split
00705 #define NVIC_APINT_PRIGROUP_2_6 0x00000500 ///< Priority group 2.6 split
00706 #define NVIC_APINT_PRIGROUP_3_5 0x00000400 ///< Priority group 3.5 split
00707 #define NVIC_APINT_PRIGROUP_4_4 0x00000300 ///< Priority group 4.4 split
00708 #define NVIC_APINT_PRIGROUP_5_3 0x00000200 ///< Priority group 5.3 split
00709 #define NVIC_APINT_PRIGROUP_6_2 0x00000100 ///< Priority group 6.2 split
00710 #define NVIC_APINT_SYSRESETREQ 0x00000004 ///< System reset request
00711 #define NVIC_APINT_VECT_CLR_ACT 0x00000002 ///< Clear active NMI/fault info
00712 #define NVIC_APINT_VECT_RESET 0x00000001 ///< System reset
00713 #define NVIC_APINT_PRIGROUP_7_1 0x00000000 ///< Priority group 7.1 split
00714
00715
00719
00720 #define NVIC_SYS_CTRL_SEVONPEND 0x00000010 ///< Wakeup on pend
00721 #define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 ///< Deep sleep enable
00722 #define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 ///< Sleep on ISR exit
00723
00724
00728
00729 #define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 ///< Ignore bus fault in NMI/fault
00730 #define NVIC_CFG_CTRL_DIV0 0x00000010 ///< Trap on divide by 0
00731 #define NVIC_CFG_CTRL_UNALIGNED 0x00000008 ///< Trap on unaligned access
00732 #define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 ///< Allow deep interrupt trigger
00733 #define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 ///< Allow main interrupt trigger
00734 #define NVIC_CFG_CTRL_BASE_THR 0x00000001 ///< Thread state control
00735
00736
00740
00741 #define NVIC_SYS_PRI1_RES_M 0xFF000000 ///< Priority of reserved handler
00742 #define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 ///< Priority of usage fault handler
00743 #define NVIC_SYS_PRI1_BUS_M 0x0000FF00 ///< Priority of bus fault handler
00744 #define NVIC_SYS_PRI1_MEM_M 0x000000FF ///< Priority of mem manage handler
00745 #define NVIC_SYS_PRI1_USAGE_S 16
00746 #define NVIC_SYS_PRI1_BUS_S 8
00747 #define NVIC_SYS_PRI1_MEM_S 0
00748
00749
00753
00754 #define NVIC_SYS_PRI2_SVC_M 0xFF000000 ///< Priority of SVCall handler
00755 #define NVIC_SYS_PRI2_RES_M 0x00FFFFFF ///< Priority of reserved handlers
00756 #define NVIC_SYS_PRI2_SVC_S 24
00757
00758
00762
00763 #define NVIC_SYS_PRI3_TICK_M 0xFF000000 ///< Priority of Sys Tick handler
00764 #define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 ///< Priority of PendSV handler
00765 #define NVIC_SYS_PRI3_RES_M 0x0000FF00 ///< Priority of reserved handler
00766 #define NVIC_SYS_PRI3_DEBUG_M 0x000000FF ///< Priority of debug handler
00767 #define NVIC_SYS_PRI3_TICK_S 24
00768 #define NVIC_SYS_PRI3_PENDSV_S 16
00769 #define NVIC_SYS_PRI3_DEBUG_S 0
00770
00771
00776
00777 #define NVIC_SYS_HND_CTRL_USAGE 0x00040000 ///< Usage fault enable
00778 #define NVIC_SYS_HND_CTRL_BUS 0x00020000 ///< Bus fault enable
00779 #define NVIC_SYS_HND_CTRL_MEM 0x00010000 ///< Mem manage fault enable
00780 #define NVIC_SYS_HND_CTRL_SVC 0x00008000 ///< SVCall is pended
00781 #define NVIC_SYS_HND_CTRL_BUSP 0x00004000 ///< Bus fault is pended
00782 #define NVIC_SYS_HND_CTRL_TICK 0x00000800 ///< Sys tick is active
00783 #define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 ///< PendSV is active
00784 #define NVIC_SYS_HND_CTRL_MON 0x00000100 ///< Monitor is active
00785 #define NVIC_SYS_HND_CTRL_SVCA 0x00000080 ///< SVCall is active
00786 #define NVIC_SYS_HND_CTRL_USGA 0x00000008 ///< Usage fault is active
00787 #define NVIC_SYS_HND_CTRL_BUSA 0x00000002 ///< Bus fault is active
00788 #define NVIC_SYS_HND_CTRL_MEMA 0x00000001 ///< Mem manage is active
00789
00790
00795
00796 #define NVIC_FAULT_STAT_DIV0 0x02000000 ///< Divide by zero fault
00797 #define NVIC_FAULT_STAT_UNALIGN 0x01000000 ///< Unaligned access fault
00798 #define NVIC_FAULT_STAT_NOCP 0x00080000 ///< No coprocessor fault
00799 #define NVIC_FAULT_STAT_INVPC 0x00040000 ///< Invalid PC fault
00800 #define NVIC_FAULT_STAT_INVSTAT 0x00020000 ///< Invalid state fault
00801 #define NVIC_FAULT_STAT_UNDEF 0x00010000 ///< Undefined instruction fault
00802 #define NVIC_FAULT_STAT_BFARV 0x00008000 ///< BFAR is valid
00803 #define NVIC_FAULT_STAT_BSTKE 0x00001000 ///< Stack bus fault
00804 #define NVIC_FAULT_STAT_BUSTKE 0x00000800 ///< Unstack bus fault
00805 #define NVIC_FAULT_STAT_IMPRE 0x00000400 ///< Imprecise data bus error
00806 #define NVIC_FAULT_STAT_PRECISE 0x00000200 ///< Precise data bus error
00807 #define NVIC_FAULT_STAT_IBUS 0x00000100 ///< Instruction bus fault
00808 #define NVIC_FAULT_STAT_MMARV 0x00000080 ///< MMAR is valid
00809 #define NVIC_FAULT_STAT_MSTKE 0x00000010 ///< Stack access violation
00810 #define NVIC_FAULT_STAT_MUSTKE 0x00000008 ///< Unstack access violation
00811 #define NVIC_FAULT_STAT_DERR 0x00000002 ///< Data access violation
00812 #define NVIC_FAULT_STAT_IERR 0x00000001 ///< Instruction access violation
00813
00814
00819
00820 #define NVIC_HFAULT_STAT_DBG 0x80000000 ///< Debug event
00821 #define NVIC_HFAULT_STAT_FORCED 0x40000000 ///< Cannot execute fault handler
00822 #define NVIC_HFAULT_STAT_VECT 0x00000002 ///< Vector table read fault
00823
00824
00829
00830 #define NVIC_DEBUG_STAT_EXTRNL 0x00000010 ///< EDBGRQ asserted
00831 #define NVIC_DEBUG_STAT_VCATCH 0x00000008 ///< Vector catch
00832 #define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 ///< DWT match
00833 #define NVIC_DEBUG_STAT_BKPT 0x00000002 ///< Breakpoint instruction
00834 #define NVIC_DEBUG_STAT_HALTED 0x00000001 ///< Halt request
00835
00836
00840
00841 #define NVIC_MM_ADDR_M 0xFFFFFFFF ///< Data fault address
00842 #define NVIC_MM_ADDR_S 0
00843
00844
00849
00850 #define NVIC_FAULT_ADDR_M 0xFFFFFFFF ///< Data bus fault address
00851 #define NVIC_FAULT_ADDR_S 0
00852
00853
00857
00858 #define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 ///< Number of I regions
00859 #define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 ///< Number of D regions
00860 #define NVIC_MPU_TYPE_SEPARATE 0x00000001 ///< Separate or unified MPU
00861 #define NVIC_MPU_TYPE_IREGION_S 16
00862 #define NVIC_MPU_TYPE_DREGION_S 8
00863
00864
00868
00869 #define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 ///< MPU default region in priv mode
00870 #define NVIC_MPU_CTRL_HFNMIENA 0x00000002 ///< MPU enabled during faults
00871 #define NVIC_MPU_CTRL_ENABLE 0x00000001 ///< MPU enable
00872
00873
00878
00879 #define NVIC_MPU_NUMBER_M 0x000000FF ///< MPU region to access
00880 #define NVIC_MPU_NUMBER_S 0
00881
00882
00886
00887 #define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 ///< Base address mask
00888 #define NVIC_MPU_BASE_VALID 0x00000010 ///< Region number valid
00889 #define NVIC_MPU_BASE_REGION_M 0x0000000F ///< Region number
00890 #define NVIC_MPU_BASE_ADDR_S 8
00891 #define NVIC_MPU_BASE_REGION_S 0
00892
00893
00897
00898 #define NVIC_MPU_ATTR_M 0xFFFF0000 ///< Attributes
00899 #define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 ///< prv: no access, usr: no access
00900 #define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 ///< Bufferable
00901 #define NVIC_MPU_ATTR_CACHEABLE 0x00020000 ///< Cacheable
00902 #define NVIC_MPU_ATTR_SHAREABLE 0x00040000 ///< Shareable
00903 #define NVIC_MPU_ATTR_TEX_M 0x00380000 ///< Type extension mask
00904 #define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 ///< prv: rw, usr: none
00905 #define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 ///< prv: rw, usr: read-only
00906 #define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 ///< prv: rw, usr: rw
00907 #define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 ///< prv: ro, usr: none
00908 #define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 ///< prv: ro, usr: ro
00909 #define NVIC_MPU_ATTR_AP_M 0x07000000 ///< Access permissions mask
00910 #define NVIC_MPU_ATTR_XN 0x10000000 ///< Execute disable
00911 #define NVIC_MPU_ATTR_SRD_M 0x0000FF00 ///< Sub-region disable mask
00912 #define NVIC_MPU_ATTR_SRD_0 0x00000100 ///< Sub-region 0 disable
00913 #define NVIC_MPU_ATTR_SRD_1 0x00000200 ///< Sub-region 1 disable
00914 #define NVIC_MPU_ATTR_SRD_2 0x00000400 ///< Sub-region 2 disable
00915 #define NVIC_MPU_ATTR_SRD_3 0x00000800 ///< Sub-region 3 disable
00916 #define NVIC_MPU_ATTR_SRD_4 0x00001000 ///< Sub-region 4 disable
00917 #define NVIC_MPU_ATTR_SRD_5 0x00002000 ///< Sub-region 5 disable
00918 #define NVIC_MPU_ATTR_SRD_6 0x00004000 ///< Sub-region 6 disable
00919 #define NVIC_MPU_ATTR_SRD_7 0x00008000 ///< Sub-region 7 disable
00920 #define NVIC_MPU_ATTR_SIZE_M 0x0000003E ///< Region size mask
00921 #define NVIC_MPU_ATTR_SIZE_32B 0x00000008 ///< Region size 32 bytes
00922 #define NVIC_MPU_ATTR_SIZE_64B 0x0000000A ///< Region size 64 bytes
00923 #define NVIC_MPU_ATTR_SIZE_128B 0x0000000C ///< Region size 128 bytes
00924 #define NVIC_MPU_ATTR_SIZE_256B 0x0000000E ///< Region size 256 bytes
00925 #define NVIC_MPU_ATTR_SIZE_512B 0x00000010 ///< Region size 512 bytes
00926 #define NVIC_MPU_ATTR_SIZE_1K 0x00000012 ///< Region size 1 Kbytes
00927 #define NVIC_MPU_ATTR_SIZE_2K 0x00000014 ///< Region size 2 Kbytes
00928 #define NVIC_MPU_ATTR_SIZE_4K 0x00000016 ///< Region size 4 Kbytes
00929 #define NVIC_MPU_ATTR_SIZE_8K 0x00000018 ///< Region size 8 Kbytes
00930 #define NVIC_MPU_ATTR_SIZE_16K 0x0000001A ///< Region size 16 Kbytes
00931 #define NVIC_MPU_ATTR_SIZE_32K 0x0000001C ///< Region size 32 Kbytes
00932 #define NVIC_MPU_ATTR_SIZE_64K 0x0000001E ///< Region size 64 Kbytes
00933 #define NVIC_MPU_ATTR_SIZE_128K 0x00000020 ///< Region size 128 Kbytes
00934 #define NVIC_MPU_ATTR_SIZE_256K 0x00000022 ///< Region size 256 Kbytes
00935 #define NVIC_MPU_ATTR_SIZE_512K 0x00000024 ///< Region size 512 Kbytes
00936 #define NVIC_MPU_ATTR_SIZE_1M 0x00000026 ///< Region size 1 Mbytes
00937 #define NVIC_MPU_ATTR_SIZE_2M 0x00000028 ///< Region size 2 Mbytes
00938 #define NVIC_MPU_ATTR_SIZE_4M 0x0000002A ///< Region size 4 Mbytes
00939 #define NVIC_MPU_ATTR_SIZE_8M 0x0000002C ///< Region size 8 Mbytes
00940 #define NVIC_MPU_ATTR_SIZE_16M 0x0000002E ///< Region size 16 Mbytes
00941 #define NVIC_MPU_ATTR_SIZE_32M 0x00000030 ///< Region size 32 Mbytes
00942 #define NVIC_MPU_ATTR_SIZE_64M 0x00000032 ///< Region size 64 Mbytes
00943 #define NVIC_MPU_ATTR_SIZE_128M 0x00000034 ///< Region size 128 Mbytes
00944 #define NVIC_MPU_ATTR_SIZE_256M 0x00000036 ///< Region size 256 Mbytes
00945 #define NVIC_MPU_ATTR_SIZE_512M 0x00000038 ///< Region size 512 Mbytes
00946 #define NVIC_MPU_ATTR_SIZE_1G 0x0000003A ///< Region size 1 Gbytes
00947 #define NVIC_MPU_ATTR_SIZE_2G 0x0000003C ///< Region size 2 Gbytes
00948 #define NVIC_MPU_ATTR_SIZE_4G 0x0000003E ///< Region size 4 Gbytes
00949 #define NVIC_MPU_ATTR_ENABLE 0x00000001 ///< Region enable
00950
00951
00955
00956 #define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 ///< Debug key mask
00957 #define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 ///< Debug key
00958 #define NVIC_DBG_CTRL_S_RESET_ST \
00959 0x02000000 ///< Core has reset since last read
00960 #define NVIC_DBG_CTRL_S_RETIRE_ST \
00961 0x01000000 ///< Core has executed insruction
00962
00963 #define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 ///< Core is locked up
00964 #define NVIC_DBG_CTRL_S_SLEEP 0x00040000 ///< Core is sleeping
00965 #define NVIC_DBG_CTRL_S_HALT 0x00020000 ///< Core status on halt
00966 #define NVIC_DBG_CTRL_S_REGRDY 0x00010000 ///< Register read/write available
00967 #define NVIC_DBG_CTRL_C_SNAPSTALL \
00968 0x00000020 ///< Breaks a stalled load/store
00969 #define NVIC_DBG_CTRL_C_MASKINT 0x00000008 ///< Mask interrupts when stepping
00970 #define NVIC_DBG_CTRL_C_STEP 0x00000004 ///< Step the core
00971 #define NVIC_DBG_CTRL_C_HALT 0x00000002 ///< Halt the core
00972 #define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 ///< Enable debug
00973
00974
00978
00979 #define NVIC_DBG_XFER_REG_WNR 0x00010000 ///< Write or not read
00980 #define NVIC_DBG_XFER_REG_SEL_M 0x0000001F ///< Register
00981 #define NVIC_DBG_XFER_REG_CFBP 0x00000014 ///< Control/Fault/BasePri/PriMask
00982 #define NVIC_DBG_XFER_REG_DSP 0x00000013 ///< Deep SP
00983 #define NVIC_DBG_XFER_REG_PSP 0x00000012 ///< Process SP
00984 #define NVIC_DBG_XFER_REG_MSP 0x00000011 ///< Main SP
00985 #define NVIC_DBG_XFER_REG_FLAGS 0x00000010 ///< xPSR/Flags register
00986 #define NVIC_DBG_XFER_REG_R15 0x0000000F ///< Register R15
00987 #define NVIC_DBG_XFER_REG_R14 0x0000000E ///< Register R14
00988 #define NVIC_DBG_XFER_REG_R13 0x0000000D ///< Register R13
00989 #define NVIC_DBG_XFER_REG_R12 0x0000000C ///< Register R12
00990 #define NVIC_DBG_XFER_REG_R11 0x0000000B ///< Register R11
00991 #define NVIC_DBG_XFER_REG_R10 0x0000000A ///< Register R10
00992 #define NVIC_DBG_XFER_REG_R9 0x00000009 ///< Register R9
00993 #define NVIC_DBG_XFER_REG_R8 0x00000008 ///< Register R8
00994 #define NVIC_DBG_XFER_REG_R7 0x00000007 ///< Register R7
00995 #define NVIC_DBG_XFER_REG_R6 0x00000006 ///< Register R6
00996 #define NVIC_DBG_XFER_REG_R5 0x00000005 ///< Register R5
00997 #define NVIC_DBG_XFER_REG_R4 0x00000004 ///< Register R4
00998 #define NVIC_DBG_XFER_REG_R3 0x00000003 ///< Register R3
00999 #define NVIC_DBG_XFER_REG_R2 0x00000002 ///< Register R2
01000 #define NVIC_DBG_XFER_REG_R1 0x00000001 ///< Register R1
01001 #define NVIC_DBG_XFER_REG_R0 0x00000000 ///< Register R0
01002
01003
01007
01008 #define NVIC_DBG_DATA_M 0xFFFFFFFF ///< Data temporary cache
01009 #define NVIC_DBG_DATA_S 0
01010
01011
01015
01016 #define NVIC_DBG_INT_HARDERR 0x00000400 ///< Debug trap on hard fault
01017 #define NVIC_DBG_INT_INTERR 0x00000200 ///< Debug trap on interrupt errors
01018 #define NVIC_DBG_INT_BUSERR 0x00000100 ///< Debug trap on bus error
01019 #define NVIC_DBG_INT_STATERR 0x00000080 ///< Debug trap on usage fault state
01020 #define NVIC_DBG_INT_CHKERR 0x00000040 ///< Debug trap on usage fault check
01021 #define NVIC_DBG_INT_NOCPERR 0x00000020 ///< Debug trap on coprocessor error
01022 #define NVIC_DBG_INT_MMERR 0x00000010 ///< Debug trap on mem manage fault
01023 #define NVIC_DBG_INT_RESET 0x00000008 ///< Core reset status
01024 #define NVIC_DBG_INT_RSTPENDCLR 0x00000004 ///< Clear pending core reset
01025 #define NVIC_DBG_INT_RSTPENDING 0x00000002 ///< Core reset is pending
01026 #define NVIC_DBG_INT_RSTVCATCH 0x00000001 ///< Reset vector catch
01027
01028
01032
01033 #define NVIC_SW_TRIG_INTID_M 0x000003FF ///< Interrupt to trigger
01034 #define NVIC_SW_TRIG_INTID_S 0
01035
01036
01037 #endif
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