lm3s_pwm.h
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00036 #ifndef L3MS_PWM_H
00037 #define L3MS_PWM_H
00038
00042 #define PWM_O_CTL (*((reg32_t *)(PWMC_BASE + 0x00000000))) //< PWM Master Control
00043 #define PWM_O_SYNC (*((reg32_t *)(PWMC_BASE + 0x00000004))) //< PWM Time Base Sync
00044 #define PWM_O_ENABLE (*((reg32_t *)(PWMC_BASE + 0x00000008))) //< PWM Output Enable
00045 #define PWM_O_INVERT (*((reg32_t *)(PWMC_BASE + 0x0000000C))) //< PWM Output Inversion
00046 #define PWM_O_FAULT (*((reg32_t *)(PWMC_BASE + 0x00000010))) //< PWM Output Fault
00047 #define PWM_O_INTEN (*((reg32_t *)(PWMC_BASE + 0x00000014))) //< PWM Interrupt Enable
00048 #define PWM_O_RIS (*((reg32_t *)(PWMC_BASE + 0x00000018))) //< PWM Raw Interrupt Status
00049 #define PWM_O_ISC (*((reg32_t *)(PWMC_BASE + 0x0000001C))) //< PWM Interrupt Status and Clear
00050 #define PWM_O_STATUS (*((reg32_t *)(PWMC_BASE + 0x00000020))) //< PWM Status
00051 #define PWM_O_FAULTVAL (*((reg32_t *)(PWMC_BASE + 0x00000024))) //< PWM Fault Condition Value
00052 #define PWM_O_ENUPD (*((reg32_t *)(PWMC_BASE + 0x00000028))) //< PWM Enable Update
00053 #define PWM_O_0_CTL (*((reg32_t *)(PWMC_BASE + 0x00000040))) //< PWM0 Control
00054 #define PWM_O_0_INTEN (*((reg32_t *)(PWMC_BASE + 0x00000044))) //< PWM0 Interrupt and Trigger Enable
00055 #define PWM_O_0_RIS (*((reg32_t *)(PWMC_BASE + 0x00000048))) //< PWM0 Raw Interrupt Status
00056 #define PWM_O_0_ISC (*((reg32_t *)(PWMC_BASE + 0x0000004C))) //< PWM0 Interrupt Status and Clear
00057 #define PWM_O_0_LOAD (*((reg32_t *)(PWMC_BASE + 0x00000050))) //< PWM0 Load
00058 #define PWM_O_0_COUNT (*((reg32_t *)(PWMC_BASE + 0x00000054))) //< PWM0 Counter
00059 #define PWM_O_0_CMPA (*((reg32_t *)(PWMC_BASE + 0x00000058))) //< PWM0 Compare A
00060 #define PWM_O_0_CMPB (*((reg32_t *)(PWMC_BASE + 0x0000005C))) //< PWM0 Compare B
00061 #define PWM_O_0_GENA (*((reg32_t *)(PWMC_BASE + 0x00000060))) //< PWM0 Generator A Control
00062 #define PWM_O_0_GENB (*((reg32_t *)(PWMC_BASE + 0x00000064))) //< PWM0 Generator B Control
00063 #define PWM_O_0_DBCTL (*((reg32_t *)(PWMC_BASE + 0x00000068))) //< PWM0 Dead-Band Control
00064 #define PWM_O_0_DBRISE (*((reg32_t *)(PWMC_BASE + 0x0000006C))) //< PWM0 Dead-Band Rising-Edge Delay
00065 #define PWM_O_0_DBFALL (*((reg32_t *)(PWMC_BASE + 0x00000070))) //< PWM0 Dead-Band Falling-Edge-Delay
00066 #define PWM_O_0_FLTSRC0 (*((reg32_t *)(PWMC_BASE + 0x00000074))) //< PWM0 Fault Source 0
00067 #define PWM_O_0_FLTSRC1 (*((reg32_t *)(PWMC_BASE + 0x00000078))) //< PWM0 Fault Source 1
00068 #define PWM_O_0_MINFLTPER (*((reg32_t *)(PWMC_BASE + 0x0000007C))) //< PWM0 Minimum Fault Period
00069 #define PWM_O_1_CTL (*((reg32_t *)(PWMC_BASE + 0x00000080))) //< PWM1 Control
00070 #define PWM_O_1_INTEN (*((reg32_t *)(PWMC_BASE + 0x00000084))) //< PWM1 Interrupt and Trigger Enable
00071 #define PWM_O_1_RIS (*((reg32_t *)(PWMC_BASE + 0x00000088))) //< PWM1 Raw Interrupt Status
00072 #define PWM_O_1_ISC (*((reg32_t *)(PWMC_BASE + 0x0000008C))) //< PWM1 Interrupt Status and Clear
00073 #define PWM_O_1_LOAD (*((reg32_t *)(PWMC_BASE + 0x00000090))) //< PWM1 Load
00074 #define PWM_O_1_COUNT (*((reg32_t *)(PWMC_BASE + 0x00000094))) //< PWM1 Counter
00075 #define PWM_O_1_CMPA (*((reg32_t *)(PWMC_BASE + 0x00000098))) //< PWM1 Compare A
00076 #define PWM_O_1_CMPB (*((reg32_t *)(PWMC_BASE + 0x0000009C))) //< PWM1 Compare B
00077 #define PWM_O_1_GENA (*((reg32_t *)(PWMC_BASE + 0x000000A0))) //< PWM1 Generator A Control
00078 #define PWM_O_1_GENB (*((reg32_t *)(PWMC_BASE + 0x000000A4))) //< PWM1 Generator B Control
00079 #define PWM_O_1_DBCTL (*((reg32_t *)(PWMC_BASE + 0x000000A8))) //< PWM1 Dead-Band Control
00080 #define PWM_O_1_DBRISE (*((reg32_t *)(PWMC_BASE + 0x000000AC))) //< PWM1 Dead-Band Rising-Edge Delay
00081 #define PWM_O_1_DBFALL (*((reg32_t *)(PWMC_BASE + 0x000000B0))) //< PWM1 Dead-Band Falling-Edge-Delay
00082 #define PWM_O_1_FLTSRC0 (*((reg32_t *)(PWMC_BASE + 0x000000B4))) //< PWM1 Fault Source 0
00083 #define PWM_O_1_FLTSRC1 (*((reg32_t *)(PWMC_BASE + 0x000000B8))) //< PWM1 Fault Source 1
00084 #define PWM_O_1_MINFLTPER (*((reg32_t *)(PWMC_BASE + 0x000000BC))) //< PWM1 Minimum Fault Period
00085 #define PWM_O_2_CTL (*((reg32_t *)(PWMC_BASE + 0x000000C0))) //< PWM2 Control
00086 #define PWM_O_2_INTEN (*((reg32_t *)(PWMC_BASE + 0x000000C4))) //< PWM2 Interrupt and Trigger Enable
00087 #define PWM_O_2_RIS (*((reg32_t *)(PWMC_BASE + 0x000000C8))) //< PWM2 Raw Interrupt Status
00088 #define PWM_O_2_ISC (*((reg32_t *)(PWMC_BASE + 0x000000CC))) //< PWM2 Interrupt Status and Clear
00089 #define PWM_O_2_LOAD (*((reg32_t *)(PWMC_BASE + 0x000000D0))) //< PWM2 Load
00090 #define PWM_O_2_COUNT (*((reg32_t *)(PWMC_BASE + 0x000000D4))) //< PWM2 Counter
00091 #define PWM_O_2_CMPA (*((reg32_t *)(PWMC_BASE + 0x000000D8))) //< PWM2 Compare A
00092 #define PWM_O_2_CMPB (*((reg32_t *)(PWMC_BASE + 0x000000DC))) //< PWM2 Compare B
00093 #define PWM_O_2_GENA (*((reg32_t *)(PWMC_BASE + 0x000000E0))) //< PWM2 Generator A Control
00094 #define PWM_O_2_GENB (*((reg32_t *)(PWMC_BASE + 0x000000E4))) //< PWM2 Generator B Control
00095 #define PWM_O_2_DBCTL (*((reg32_t *)(PWMC_BASE + 0x000000E8))) //< PWM2 Dead-Band Control
00096 #define PWM_O_2_DBRISE (*((reg32_t *)(PWMC_BASE + 0x000000EC))) //< PWM2 Dead-Band Rising-Edge Delay
00097 #define PWM_O_2_DBFALL (*((reg32_t *)(PWMC_BASE + 0x000000F0))) //< PWM2 Dead-Band Falling-Edge-Delay
00098 #define PWM_O_2_FLTSRC0 (*((reg32_t *)(PWMC_BASE + 0x000000F4))) //< PWM2 Fault Source 0
00099 #define PWM_O_2_FLTSRC1 (*((reg32_t *)(PWMC_BASE + 0x000000F8))) //< PWM2 Fault Source 1
00100 #define PWM_O_2_MINFLTPER (*((reg32_t *)(PWMC_BASE + 0x000000FC))) //< PWM2 Minimum Fault Period
00101 #define PWM_O_3_CTL (*((reg32_t *)(PWMC_BASE + 0x00000100))) //< PWM3 Control
00102 #define PWM_O_3_INTEN (*((reg32_t *)(PWMC_BASE + 0x00000104))) //< PWM3 Interrupt and Trigger Enable
00103 #define PWM_O_3_RIS (*((reg32_t *)(PWMC_BASE + 0x00000108))) //< PWM3 Raw Interrupt Status
00104 #define PWM_O_3_ISC (*((reg32_t *)(PWMC_BASE + 0x0000010C))) //< PWM3 Interrupt Status and Clear
00105 #define PWM_O_3_LOAD (*((reg32_t *)(PWMC_BASE + 0x00000110))) //< PWM3 Load
00106 #define PWM_O_3_COUNT (*((reg32_t *)(PWMC_BASE + 0x00000114))) //< PWM3 Counter
00107 #define PWM_O_3_CMPA (*((reg32_t *)(PWMC_BASE + 0x00000118))) //< PWM3 Compare A
00108 #define PWM_O_3_CMPB (*((reg32_t *)(PWMC_BASE + 0x0000011C))) //< PWM3 Compare B
00109 #define PWM_O_3_GENA (*((reg32_t *)(PWMC_BASE + 0x00000120))) //< PWM3 Generator A Control
00110 #define PWM_O_3_GENB (*((reg32_t *)(PWMC_BASE + 0x00000124))) //< PWM3 Generator B Control
00111 #define PWM_O_3_DBCTL (*((reg32_t *)(PWMC_BASE + 0x00000128))) //< PWM3 Dead-Band Control
00112 #define PWM_O_3_DBRISE (*((reg32_t *)(PWMC_BASE + 0x0000012C))) //< PWM3 Dead-Band Rising-Edge Delay
00113 #define PWM_O_3_DBFALL (*((reg32_t *)(PWMC_BASE + 0x00000130))) //< PWM3 Dead-Band Falling-Edge-Delay
00114 #define PWM_O_3_FLTSRC0 (*((reg32_t *)(PWMC_BASE + 0x00000134))) //< PWM3 Fault Source 0
00115 #define PWM_O_3_FLTSRC1 (*((reg32_t *)(PWMC_BASE + 0x00000138))) //< PWM3 Fault Source 1
00116 #define PWM_O_3_MINFLTPER (*((reg32_t *)(PWMC_BASE + 0x0000013C))) //< PWM3 Minimum Fault Period
00117 #define PWM_O_0_FLTSEN (*((reg32_t *)(PWMC_BASE + 0x00000800))) //< PWM0 Fault Pin Logic Sense
00118 #define PWM_O_0_FLTSTAT0 (*((reg32_t *)(PWMC_BASE + 0x00000804))) //< PWM0 Fault Status 0
00119 #define PWM_O_0_FLTSTAT1 (*((reg32_t *)(PWMC_BASE + 0x00000808))) //< PWM0 Fault Status 1
00120 #define PWM_O_1_FLTSEN (*((reg32_t *)(PWMC_BASE + 0x00000880))) //< PWM1 Fault Pin Logic Sense
00121 #define PWM_O_1_FLTSTAT0 (*((reg32_t *)(PWMC_BASE + 0x00000884))) //< PWM1 Fault Status 0
00122 #define PWM_O_1_FLTSTAT1 (*((reg32_t *)(PWMC_BASE + 0x00000888))) //< PWM1 Fault Status 1
00123 #define PWM_O_2_FLTSEN (*((reg32_t *)(PWMC_BASE + 0x00000900))) //< PWM2 Fault Pin Logic Sense
00124 #define PWM_O_2_FLTSTAT0 (*((reg32_t *)(PWMC_BASE + 0x00000904))) //< PWM2 Fault Status 0
00125 #define PWM_O_2_FLTSTAT1 (*((reg32_t *)(PWMC_BASE + 0x00000908))) //< PWM2 Fault Status 1
00126 #define PWM_O_3_FLTSEN (*((reg32_t *)(PWMC_BASE + 0x00000980))) //< PWM3 Fault Pin Logic Sense
00127 #define PWM_O_3_FLTSTAT0 (*((reg32_t *)(PWMC_BASE + 0x00000984))) //< PWM3 Fault Status 0
00128 #define PWM_O_3_FLTSTAT1 (*((reg32_t *)(PWMC_BASE + 0x00000988))) //< PWM3 Fault Status 1
00129
00133 #define PWM_CTL_GLOBALSYNC3 3 //< Update PWM Generator 3
00134 #define PWM_CTL_GLOBALSYNC2 2 //< Update PWM Generator 2
00135 #define PWM_CTL_GLOBALSYNC1 1 //< Update PWM Generator 1
00136 #define PWM_CTL_GLOBALSYNC0 0 //< Update PWM Generator 0
00137
00141 #define PWM_SYNC_SYNC3 3 //< Reset Generator 3 Counter
00142 #define PWM_SYNC_SYNC2 2 //< Reset Generator 2 Counter
00143 #define PWM_SYNC_SYNC1 1 //< Reset Generator 1 Counter
00144 #define PWM_SYNC_SYNC0 0 //< Reset Generator 0 Counter
00145
00149 #define PWM_ENABLE_PWM7EN 7 //< PWM7 Output Enable
00150 #define PWM_ENABLE_PWM6EN 6 //< PWM6 Output Enable
00151 #define PWM_ENABLE_PWM5EN 5 //< PWM5 Output Enable
00152 #define PWM_ENABLE_PWM4EN 4 //< PWM4 Output Enable
00153 #define PWM_ENABLE_PWM3EN 3 //< PWM3 Output Enable
00154 #define PWM_ENABLE_PWM2EN 2 //< PWM2 Output Enable
00155 #define PWM_ENABLE_PWM1EN 1 //< PWM1 Output Enable
00156 #define PWM_ENABLE_PWM0EN 0 //< PWM0 Output Enable
00157
00161 #define PWM_INVERT_PWM7INV 7 //< Invert PWM7 Signal
00162 #define PWM_INVERT_PWM6INV 6 //< Invert PWM6 Signal
00163 #define PWM_INVERT_PWM5INV 5 //< Invert PWM5 Signal
00164 #define PWM_INVERT_PWM4INV 4 //< Invert PWM4 Signal
00165 #define PWM_INVERT_PWM3INV 3 //< Invert PWM3 Signal
00166 #define PWM_INVERT_PWM2INV 2 //< Invert PWM2 Signal
00167 #define PWM_INVERT_PWM1INV 1 //< Invert PWM1 Signal
00168 #define PWM_INVERT_PWM0INV 0 //< Invert PWM0 Signal
00169
00173 #define PWM_FAULT_FAULT7 7 //< PWM7 Fault
00174 #define PWM_FAULT_FAULT6 6 //< PWM6 Fault
00175 #define PWM_FAULT_FAULT5 5 //< PWM5 Fault
00176 #define PWM_FAULT_FAULT4 4 //< PWM4 Fault
00177 #define PWM_FAULT_FAULT3 3 //< PWM3 Fault
00178 #define PWM_FAULT_FAULT2 2 //< PWM2 Fault
00179 #define PWM_FAULT_FAULT1 1 //< PWM1 Fault
00180 #define PWM_FAULT_FAULT0 0 //< PWM0 Fault
00181
00185 #define PWM_INTEN_INTFAULT3 19 //< Interrupt Fault 3
00186 #define PWM_INTEN_INTFAULT2 18 //< Interrupt Fault 2
00187 #define PWM_INTEN_INTFAULT1 17 //< Interrupt Fault 1
00188 #define PWM_INTEN_INTFAULT 16 //< Fault Interrupt Enable
00189 #define PWM_INTEN_INTFAULT0 16 //< Interrupt Fault 0
00190 #define PWM_INTEN_INTPWM3 3 //< PWM3 Interrupt Enable
00191 #define PWM_INTEN_INTPWM2 2 //< PWM2 Interrupt Enable
00192 #define PWM_INTEN_INTPWM1 1 //< PWM1 Interrupt Enable
00193 #define PWM_INTEN_INTPWM0 0 //< PWM0 Interrupt Enable
00194
00198 #define PWM_RIS_INTFAULT3 19 //< Interrupt Fault PWM 3
00199 #define PWM_RIS_INTFAULT2 18 //< Interrupt Fault PWM 2
00200 #define PWM_RIS_INTFAULT1 17 //< Interrupt Fault PWM 1
00201 #define PWM_RIS_INTFAULT0 16 //< Interrupt Fault PWM 0
00202 #define PWM_RIS_INTFAULT 16 //< Fault Interrupt Asserted
00203 #define PWM_RIS_INTPWM3 3 //< PWM3 Interrupt Asserted
00204 #define PWM_RIS_INTPWM2 2 //< PWM2 Interrupt Asserted
00205 #define PWM_RIS_INTPWM1 1 //< PWM1 Interrupt Asserted
00206 #define PWM_RIS_INTPWM0 0 //< PWM0 Interrupt Asserted
00207
00211 #define PWM_ISC_INTFAULT3 19 //< FAULT3 Interrupt Asserted
00212 #define PWM_ISC_INTFAULT2 18 //< FAULT2 Interrupt Asserted
00213 #define PWM_ISC_INTFAULT1 17 //< FAULT1 Interrupt Asserted
00214 #define PWM_ISC_INTFAULT 16 //< Fault Interrupt Asserted
00215 #define PWM_ISC_INTFAULT0 16 //< FAULT0 Interrupt Asserted
00216 #define PWM_ISC_INTPWM3 3 //< PWM3 Interrupt Status
00217 #define PWM_ISC_INTPWM2 2 //< PWM2 Interrupt Status
00218 #define PWM_ISC_INTPWM1 1 //< PWM1 Interrupt Status
00219 #define PWM_ISC_INTPWM0 0 //< PWM0 Interrupt Status
00220
00224 #define PWM_STATUS_FAULT3 3 //< Generator 3 Fault Status
00225 #define PWM_STATUS_FAULT2 2 //< Generator 2 Fault Status
00226 #define PWM_STATUS_FAULT1 1 //< Generator 1 Fault Status
00227 #define PWM_STATUS_FAULT0 0 //< Generator 0 Fault Status
00228
00232 #define PWM_FAULTVAL_PWM7 7 //< PWM7 Fault Value
00233 #define PWM_FAULTVAL_PWM6 6 //< PWM6 Fault Value
00234 #define PWM_FAULTVAL_PWM5 5 //< PWM5 Fault Value
00235 #define PWM_FAULTVAL_PWM4 4 //< PWM4 Fault Value
00236 #define PWM_FAULTVAL_PWM3 3 //< PWM3 Fault Value
00237 #define PWM_FAULTVAL_PWM2 2 //< PWM2 Fault Value
00238 #define PWM_FAULTVAL_PWM1 1 //< PWM1 Fault Value
00239 #define PWM_FAULTVAL_PWM0 0 //< PWM0 Fault Value
00240
00244 #define PWM_ENUPD_ENUPD7_M 0x0000C000 //< PWM7 Enable Update Mode
00245 #define PWM_ENUPD_ENUPD7_IMM 0x00000000 //< Immediate
00246 #define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 //< Locally Synchronized
00247 #define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 //< Globally Synchronized
00248 #define PWM_ENUPD_ENUPD6_M 0x00003000 //< PWM6 Enable Update Mode
00249 #define PWM_ENUPD_ENUPD6_IMM 0x00000000 //< Immediate
00250 #define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 //< Locally Synchronized
00251 #define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 //< Globally Synchronized
00252 #define PWM_ENUPD_ENUPD5_M 0x00000C00 //< PWM5 Enable Update Mode
00253 #define PWM_ENUPD_ENUPD5_IMM 0x00000000 //< Immediate
00254 #define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 //< Locally Synchronized
00255 #define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 //< Globally Synchronized
00256 #define PWM_ENUPD_ENUPD4_M 0x00000300 //< PWM4 Enable Update Mode
00257 #define PWM_ENUPD_ENUPD4_IMM 0x00000000 //< Immediate
00258 #define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 //< Locally Synchronized
00259 #define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 //< Globally Synchronized
00260 #define PWM_ENUPD_ENUPD3_M 0x000000C0 //< PWM3 Enable Update Mode
00261 #define PWM_ENUPD_ENUPD3_IMM 0x00000000 //< Immediate
00262 #define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 //< Locally Synchronized
00263 #define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 //< Globally Synchronized
00264 #define PWM_ENUPD_ENUPD2_M 0x00000030 //< PWM2 Enable Update Mode
00265 #define PWM_ENUPD_ENUPD2_IMM 0x00000000 //< Immediate
00266 #define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 //< Locally Synchronized
00267 #define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 //< Globally Synchronized
00268 #define PWM_ENUPD_ENUPD1_M 0x0000000C //< PWM1 Enable Update Mode
00269 #define PWM_ENUPD_ENUPD1_IMM 0x00000000 //< Immediate
00270 #define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 //< Locally Synchronized
00271 #define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C //< Globally Synchronized
00272 #define PWM_ENUPD_ENUPD0_M 0x00000003 //< PWM0 Enable Update Mode
00273 #define PWM_ENUPD_ENUPD0_IMM 0x00000000 //< Immediate
00274 #define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 //< Locally Synchronized
00275 #define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 //< Globally Synchronized
00276
00280 #define PWM_X_CTL_LATCH 0x00040000 //< Latch Fault Input
00281 #define PWM_X_CTL_MINFLTPER 0x00020000 //< Minimum Fault Period
00282 #define PWM_X_CTL_FLTSRC 0x00010000 //< Fault Condition Source
00283 #define PWM_X_CTL_DBFALLUPD_M 0x0000C000 //< PWMnDBFALL Update Mode
00284 #define PWM_X_CTL_DBFALLUPD_I 0x00000000 //< Immediate
00285 #define PWM_X_CTL_DBFALLUPD_LS 0x00008000 //< Locally Synchronized
00286 #define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 //< Globally Synchronized
00287 #define PWM_X_CTL_DBRISEUPD_M 0x00003000 //< PWMnDBRISE Update Mode
00288 #define PWM_X_CTL_DBRISEUPD_I 0x00000000 //< Immediate
00289 #define PWM_X_CTL_DBRISEUPD_LS 0x00002000 //< Locally Synchronized
00290 #define PWM_X_CTL_DBRISEUPD_GS 0x00003000 //< Globally Synchronized
00291 #define PWM_X_CTL_DBCTLUPD_M 0x00000C00 //< PWMnDBCTL Update Mode
00292 #define PWM_X_CTL_DBCTLUPD_I 0x00000000 //< Immediate
00293 #define PWM_X_CTL_DBCTLUPD_LS 0x00000800 //< Locally Synchronized
00294 #define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 //< Globally Synchronized
00295 #define PWM_X_CTL_GENBUPD_M 0x00000300 //< PWMnGENB Update Mode
00296 #define PWM_X_CTL_GENBUPD_I 0x00000000 //< Immediate
00297 #define PWM_X_CTL_GENBUPD_LS 0x00000200 //< Locally Synchronized
00298 #define PWM_X_CTL_GENBUPD_GS 0x00000300 //< Globally Synchronized
00299 #define PWM_X_CTL_GENAUPD_M 0x000000C0 //< PWMnGENA Update Mode
00300 #define PWM_X_CTL_GENAUPD_I 0x00000000 //< Immediate
00301 #define PWM_X_CTL_GENAUPD_LS 0x00000080 //< Locally Synchronized
00302 #define PWM_X_CTL_GENAUPD_GS 0x000000C0 //< Globally Synchronized
00303 #define PWM_X_CTL_CMPBUPD 0x00000020 //< Comparator B Update Mode
00304 #define PWM_X_CTL_CMPAUPD 0x00000010 //< Comparator A Update Mode
00305 #define PWM_X_CTL_LOADUPD 0x00000008 //< Load Register Update Mode
00306 #define PWM_X_CTL_DEBUG 0x00000004 //< Debug Mode
00307 #define PWM_X_CTL_MODE 0x00000002 //< Counter Mode
00308 #define PWM_X_CTL_ENABLE 0x00000001 //< PWM Block Enable
00309
00313 #define PWM_X_INTEN_TRCMPBD 0x00002000 //< Trigger for Counter=PWMnCMPB Down
00314 #define PWM_X_INTEN_TRCMPBU 0x00001000 //< Trigger for Counter=PWMnCMPB Up
00315 #define PWM_X_INTEN_TRCMPAD 0x00000800 //< Trigger for Counter=PWMnCMPA Down
00316 #define PWM_X_INTEN_TRCMPAU 0x00000400 //< Trigger for Counter=PWMnCMPA Up
00317 #define PWM_X_INTEN_TRCNTLOAD 0x00000200 //< Trigger for Counter=PWMnLOAD
00318 #define PWM_X_INTEN_TRCNTZERO 0x00000100 //< Trigger for Counter=0
00319 #define PWM_X_INTEN_INTCMPBD 0x00000020 //< Interrupt for Counter=PWMnCMPB Down
00320 #define PWM_X_INTEN_INTCMPBU 0x00000010 //< Interrupt for Counter=PWMnCMPB Up
00321 #define PWM_X_INTEN_INTCMPAD 0x00000008 //< Interrupt for Counter=PWMnCMPA Down
00322 #define PWM_X_INTEN_INTCMPAU 0x00000004 //< Interrupt for Counter=PWMnCMPA Up
00323 #define PWM_X_INTEN_INTCNTLOAD 0x00000002 //< Interrupt for Counter=PWMnLOAD
00324 #define PWM_X_INTEN_INTCNTZERO 0x00000001 //< Interrupt for Counter=0
00325
00329 #define PWM_X_RIS_INTCMPBD 0x00000020 //< Comparator B Down Interrupt Status
00330 #define PWM_X_RIS_INTCMPBU 0x00000010 //< Comparator B Up Interrupt Status
00331 #define PWM_X_RIS_INTCMPAD 0x00000008 //< Comparator A Down Interrupt Status
00332 #define PWM_X_RIS_INTCMPAU 0x00000004 //< Comparator A Up Interrupt Status
00333 #define PWM_X_RIS_INTCNTLOAD 0x00000002 //< Counter=Load Interrupt Status
00334 #define PWM_X_RIS_INTCNTZERO 0x00000001 //< Counter=0 Interrupt Status
00335
00339 #define PWM_X_ISC_INTCMPBD 0x00000020 //< Comparator B Down Interrupt
00340 #define PWM_X_ISC_INTCMPBU 0x00000010 //< Comparator B Up Interrupt
00341 #define PWM_X_ISC_INTCMPAD 0x00000008 //< Comparator A Down Interrupt
00342 #define PWM_X_ISC_INTCMPAU 0x00000004 //< Comparator A Up Interrupt
00343 #define PWM_X_ISC_INTCNTLOAD 0x00000002 //< Counter=Load Interrupt
00344 #define PWM_X_ISC_INTCNTZERO 0x00000001 //< Counter=0 Interrupt
00345
00349 #define PWM_X_LOAD_M 0x0000FFFF //< Counter Load Value
00350 #define PWM_X_LOAD_S 0
00351
00355 #define PWM_X_COUNT_M 0x0000FFFF //< Counter Value
00356 #define PWM_X_COUNT_S 0
00357
00361 #define PWM_X_CMPA_M 0x0000FFFF //< Comparator A Value
00362 #define PWM_X_CMPA_S 0
00363
00367 #define PWM_X_CMPB_M 0x0000FFFF //< Comparator B Value
00368 #define PWM_X_CMPB_S 0
00369
00373 #define PWM_X_GENA_ACTCMPBD_M 0x00000C00 //< Action for Comparator B Down
00374 #define PWM_X_GENA_ACTCMPBD_NONE 0x00000000 //< Do nothing
00375 #define PWM_X_GENA_ACTCMPBD_INV 0x00000400 //< Invert pwmA
00376 #define PWM_X_GENA_ACTCMPBD_ZERO 0x00000800 //< Drive pwmA Low
00377 #define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 //< Drive pwmA High
00378 #define PWM_X_GENA_ACTCMPBU_M 0x00000300 //< Action for Comparator B Up
00379 #define PWM_X_GENA_ACTCMPBU_NONE 0x00000000 //< Do nothing
00380 #define PWM_X_GENA_ACTCMPBU_INV 0x00000100 //< Invert pwmA
00381 #define PWM_X_GENA_ACTCMPBU_ZERO 0x00000200 //< Drive pwmA Low
00382 #define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 //< Drive pwmA High
00383 #define PWM_X_GENA_ACTCMPAD_M 0x000000C0 //< Action for Comparator A Down
00384 #define PWM_X_GENA_ACTCMPAD_NONE 0x00000000 //< Do nothing
00385 #define PWM_X_GENA_ACTCMPAD_INV 0x00000040 //< Invert pwmA
00386 #define PWM_X_GENA_ACTCMPAD_ZERO 0x00000080 //< Drive pwmA Low
00387 #define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 //< Drive pwmA High
00388 #define PWM_X_GENA_ACTCMPAU_M 0x00000030 //< Action for Comparator A Up
00389 #define PWM_X_GENA_ACTCMPAU_NONE 0x00000000 //< Do nothing
00390 #define PWM_X_GENA_ACTCMPAU_INV 0x00000010 //< Invert pwmA
00391 #define PWM_X_GENA_ACTCMPAU_ZERO 0x00000020 //< Drive pwmA Low
00392 #define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 //< Drive pwmA High
00393 #define PWM_X_GENA_ACTLOAD_M 0x0000000C //< Action for Counter=LOAD
00394 #define PWM_X_GENA_ACTLOAD_NONE 0x00000000 //< Do nothing
00395 #define PWM_X_GENA_ACTLOAD_INV 0x00000004 //< Invert pwmA
00396 #define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 //< Drive pwmA Low
00397 #define PWM_X_GENA_ACTLOAD_ONE 0x0000000C //< Drive pwmA High
00398 #define PWM_X_GENA_ACTZERO_M 0x00000003 //< Action for Counter=0
00399 #define PWM_X_GENA_ACTZERO_NONE 0x00000000 //< Do nothing
00400 #define PWM_X_GENA_ACTZERO_INV 0x00000001 //< Invert pwmA
00401 #define PWM_X_GENA_ACTZERO_ZERO 0x00000002 //< Drive pwmA Low
00402 #define PWM_X_GENA_ACTZERO_ONE 0x00000003 //< Drive pwmA High
00403
00407 #define PWM_X_GENB_ACTCMPBD_M 0x00000C00 //< Action for Comparator B Down
00408 #define PWM_X_GENB_ACTCMPBD_NONE 0x00000000 //< Do nothing
00409 #define PWM_X_GENB_ACTCMPBD_INV 0x00000400 //< Invert pwmB
00410 #define PWM_X_GENB_ACTCMPBD_ZERO 0x00000800 //< Drive pwmB Low
00411 #define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 //< Drive pwmB High
00412 #define PWM_X_GENB_ACTCMPBU_M 0x00000300 //< Action for Comparator B Up
00413 #define PWM_X_GENB_ACTCMPBU_NONE 0x00000000 //< Do nothing
00414 #define PWM_X_GENB_ACTCMPBU_INV 0x00000100 //< Invert pwmB
00415 #define PWM_X_GENB_ACTCMPBU_ZERO 0x00000200 //< Drive pwmB Low
00416 #define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 //< Drive pwmB High
00417 #define PWM_X_GENB_ACTCMPAD_M 0x000000C0 //< Action for Comparator A Down
00418 #define PWM_X_GENB_ACTCMPAD_NONE 0x00000000 //< Do nothing
00419 #define PWM_X_GENB_ACTCMPAD_INV 0x00000040 //< Invert pwmB
00420 #define PWM_X_GENB_ACTCMPAD_ZERO 0x00000080 //< Drive pwmB Low
00421 #define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 //< Drive pwmB High
00422 #define PWM_X_GENB_ACTCMPAU_M 0x00000030 //< Action for Comparator A Up
00423 #define PWM_X_GENB_ACTCMPAU_NONE 0x00000000 //< Do nothing
00424 #define PWM_X_GENB_ACTCMPAU_INV 0x00000010 //< Invert pwmB
00425 #define PWM_X_GENB_ACTCMPAU_ZERO 0x00000020 //< Drive pwmB Low
00426 #define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 //< Drive pwmB High
00427 #define PWM_X_GENB_ACTLOAD_M 0x0000000C //< Action for Counter=LOAD
00428 #define PWM_X_GENB_ACTLOAD_NONE 0x00000000 //< Do nothing
00429 #define PWM_X_GENB_ACTLOAD_INV 0x00000004 //< Invert pwmB
00430 #define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 //< Drive pwmB Low
00431 #define PWM_X_GENB_ACTLOAD_ONE 0x0000000C //< Drive pwmB High
00432 #define PWM_X_GENB_ACTZERO_M 0x00000003 //< Action for Counter=0
00433 #define PWM_X_GENB_ACTZERO_NONE 0x00000000 //< Do nothing
00434 #define PWM_X_GENB_ACTZERO_INV 0x00000001 //< Invert pwmB
00435 #define PWM_X_GENB_ACTZERO_ZERO 0x00000002 //< Drive pwmB Low
00436 #define PWM_X_GENB_ACTZERO_ONE 0x00000003 //< Drive pwmB High
00437
00441 #define PWM_X_DBCTL_ENABLE 0x00000001 //< Dead-Band Generator Enable
00442
00445 #define PWM_X_DBRISE_DELAY_M 0x00000FFF //< Dead-Band Rise Delay
00446 #define PWM_X_DBRISE_DELAY_S 0
00447
00451 #define PWM_X_DBFALL_DELAY_M 0x00000FFF //< Dead-Band Fall Delay
00452 #define PWM_X_DBFALL_DELAY_S 0
00453
00457 #define PWM_X_FLTSRC0_FAULT3 0x00000008 //< Fault3 Input
00458 #define PWM_X_FLTSRC0_FAULT2 0x00000004 //< Fault2 Input
00459 #define PWM_X_FLTSRC0_FAULT1 0x00000002 //< Fault1 Input
00460 #define PWM_X_FLTSRC0_FAULT0 0x00000001 //< Fault0 Input
00461
00465 #define PWM_X_FLTSRC1_DCMP7 0x00000080 //< Digital Comparator 7
00466 #define PWM_X_FLTSRC1_DCMP6 0x00000040 //< Digital Comparator 6
00467 #define PWM_X_FLTSRC1_DCMP5 0x00000020 //< Digital Comparator 5
00468 #define PWM_X_FLTSRC1_DCMP4 0x00000010 //< Digital Comparator 4
00469 #define PWM_X_FLTSRC1_DCMP3 0x00000008 //< Digital Comparator 3
00470 #define PWM_X_FLTSRC1_DCMP2 0x00000004 //< Digital Comparator 2
00471 #define PWM_X_FLTSRC1_DCMP1 0x00000002 //< Digital Comparator 1
00472 #define PWM_X_FLTSRC1_DCMP0 0x00000001 //< Digital Comparator 0
00473
00477 #define PWM_X_MINFLTPER_M 0x0000FFFF //< Minimum Fault Period
00478 #define PWM_X_MINFLTPER_S 0
00479
00483 #define PWM_X_FLTSEN_FAULT3 0x00000008 //< Fault3 Sense
00484 #define PWM_X_FLTSEN_FAULT2 0x00000004 //< Fault2 Sense
00485 #define PWM_X_FLTSEN_FAULT1 0x00000002 //< Fault1 Sense
00486 #define PWM_X_FLTSEN_FAULT0 0x00000001 //< Fault0 Sense
00487
00491 #define PWM_X_FLTSTAT0_FAULT3 0x00000008 //< Fault Input 3
00492 #define PWM_X_FLTSTAT0_FAULT2 0x00000004 //< Fault Input 2
00493 #define PWM_X_FLTSTAT0_FAULT1 0x00000002 //< Fault Input 1
00494 #define PWM_X_FLTSTAT0_FAULT0 0x00000001 //< Fault Input 0
00495
00499 #define PWM_X_FLTSTAT1_DCMP7 0x00000080 //< Digital Comparator 7 Trigger
00500 #define PWM_X_FLTSTAT1_DCMP6 0x00000040 //< Digital Comparator 6 Trigger
00501 #define PWM_X_FLTSTAT1_DCMP5 0x00000020 //< Digital Comparator 5 Trigger
00502 #define PWM_X_FLTSTAT1_DCMP4 0x00000010 //< Digital Comparator 4 Trigger
00503 #define PWM_X_FLTSTAT1_DCMP3 0x00000008 //< Digital Comparator 3 Trigger
00504 #define PWM_X_FLTSTAT1_DCMP2 0x00000004 //< Digital Comparator 2 Trigger
00505 #define PWM_X_FLTSTAT1_DCMP1 0x00000002 //< Digital Comparator 1 Trigger
00506 #define PWM_X_FLTSTAT1_DCMP0 0x00000001 //< Digital Comparator 0 Trigger
00507
00511 #define PWM_O_X_CTL (*((reg32_t *)(PWMC_BASE + 0x00000000))) //< Gen Control Reg
00512 #define PWM_O_X_INTEN (*((reg32_t *)(PWMC_BASE + 0x00000004))) //< Gen Int/Trig Enable Reg
00513 #define PWM_O_X_RIS (*((reg32_t *)(PWMC_BASE + 0x00000008))) //< Gen Raw Int Status Reg
00514 #define PWM_O_X_ISC (*((reg32_t *)(PWMC_BASE + 0x0000000C))) //< Gen Int Status Reg
00515 #define PWM_O_X_LOAD (*((reg32_t *)(PWMC_BASE + 0x00000010))) //< Gen Load Reg
00516 #define PWM_O_X_COUNT (*((reg32_t *)(PWMC_BASE + 0x00000014))) //< Gen Counter Reg
00517 #define PWM_O_X_CMPA (*((reg32_t *)(PWMC_BASE + 0x00000018))) //< Gen Compare A Reg
00518 #define PWM_O_X_CMPB (*((reg32_t *)(PWMC_BASE + 0x0000001C))) //< Gen Compare B Reg
00519 #define PWM_O_X_GENA (*((reg32_t *)(PWMC_BASE + 0x00000020))) //< Gen Generator A Ctrl Reg
00520 #define PWM_O_X_GENB (*((reg32_t *)(PWMC_BASE + 0x00000024))) //< Gen Generator B Ctrl Reg
00521 #define PWM_O_X_DBCTL (*((reg32_t *)(PWMC_BASE + 0x00000028))) //< Gen Dead Band Ctrl Reg
00522 #define PWM_O_X_DBRISE (*((reg32_t *)(PWMC_BASE + 0x0000002C))) //< Gen DB Rising Edge Delay Reg
00523 #define PWM_O_X_DBFALL (*((reg32_t *)(PWMC_BASE + 0x00000030))) //< Gen DB Falling Edge Delay Reg
00524 #define PWM_O_X_FLTSRC0 (*((reg32_t *)(PWMC_BASE + 0x00000034))) //< Fault pin, comparator condition
00525 #define PWM_O_X_FLTSRC1 (*((reg32_t *)(PWMC_BASE + 0x00000038))) //< Digital comparator condition
00526 #define PWM_O_X_MINFLTPER (*((reg32_t *)(PWMC_BASE + 0x0000003C))) //< Fault minimum period extension
00527 #define PWM_GEN_0_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000040))) //< PWM0 base
00528 #define PWM_GEN_1_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000080))) //< PWM1 base
00529 #define PWM_GEN_2_OFFSET (*((reg32_t *)(PWMC_BASE + 0x000000C0))) //< PWM2 base
00530 #define PWM_GEN_3_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000100))) //< PWM3 base
00531
00535 #define PWM_O_X_FLTSEN (*((reg32_t *)(PWMC_BASE + 0x00000000))) //< Fault logic sense
00536 #define PWM_O_X_FLTSTAT0 (*((reg32_t *)(PWMC_BASE + 0x00000004))) //< Pin and comparator status
00537 #define PWM_O_X_FLTSTAT1 (*((reg32_t *)(PWMC_BASE + 0x00000008))) //< Digital comparator status
00538 #define PWM_EXT_0_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000800))) //< PWM0 extended base
00539 #define PWM_EXT_1_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000880))) //< PWM1 extended base
00540 #define PWM_EXT_2_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000900))) //< PWM2 extended base
00541 #define PWM_EXT_3_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000980))) //< PWM3 extended base
00542
00543 #endif
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