sam3_adc.h File Reference
Go to the source code of this file.
Defines | |
| #define | ADC_BASE 0x400C0000 |
| ADC registers base. | |
| #define | ADC_SETTLING_MASK 0x00300000 |
| Analog Settling Time. | |
| #define | ADC_SETTLING_SHIFT 20 |
| Analog Settling Time shift. | |
| #define | ADC_AST3 0 |
| 3 period of ADCClock | |
| #define | ADC_AST5 1 |
| 5 period of ADCClock | |
| #define | ADC_AST9 2 |
| 9 period of ADCClock | |
| #define | ADC_AST17 3 |
| 17 period of ADCClock | |
| #define | ADC_TRACKTIM_MASK 0x0F000000 |
| Tracking Time. | |
| #define | ADC_TRACKTIM_SHIFT 24 |
| Tracking Time shift. | |
| #define | ADC_TRANSFER_MASK 0x30000000 |
| Transfer Period. | |
| #define | ADC_TRANSFER_SHIFT 28 |
| Transfer Period shift. | |
| #define | ADC_CHER_OFF 0x00000010 |
| ADC channel enable register. | |
| #define | ADC_CHER (*((reg32_t *)(ADC_BASE + ADC_CHER_OFF))) |
| Channel enable register address. | |
| #define | ADC_CHDR_OFF 0x00000014 |
| ADC channel disable register. | |
| #define | ADC_CHDR (*((reg32_t *)(ADC_BASE + ADC_CHDR_OFF))) |
| Channel disable register address. | |
| #define | ADC_CHSR_OFF 0x00000018 |
| ADC channel status register. | |
| #define | ADC_CHSR (*((reg32_t *)(ADC_BASE + ADC_CHSR_OFF))) |
| Channel status register address. | |
| #define | ADC_SR_OFF 0x0000001C |
| ADC status register. | |
| #define | ADC_SR (*((reg32_t *)(ADC_BASE + ADC_SR_OFF))) |
| Status register address. | |
| #define | ADC_CH_MASK 0x000000FF |
| Channel mask. | |
| #define | ADC_CH0 0 |
| Channel 0. | |
| #define | ADC_CH1 1 |
| Channel 1. | |
| #define | ADC_CH2 2 |
| Channel 2. | |
| #define | ADC_CH3 3 |
| Channel 3. | |
| #define | ADC_CH4 4 |
| Channel 4. | |
| #define | ADC_CH5 5 |
| Channel 5. | |
| #define | ADC_CH6 6 |
| Channel 6. | |
| #define | ADC_CH7 7 |
| Channel 7. | |
| #define | ADC_IER_OFF 0x00000024 |
| ADC Interrupt enable register. | |
| #define | ADC_IER (*((reg32_t *)(ADC_BASE + ADC_IER_OFF))) |
| Interrupt enable register. | |
| #define | ADC_IDR_OFF 0x00000028 |
| ADC Interrupt disable register. | |
| #define | ADC_IDR (*((reg32_t *)(ADC_BASE + ADC_IDR_OFF))) |
| Interrupt disable register. | |
| #define | ADC_IMR_OFF 0x0000002C |
| ADC Interrupt mask register. | |
| #define | ADC_IMR (*((reg32_t *)(ADC_BASE + ADC_IMR_OFF))) |
| Interrupt mask register. | |
| #define | ADC_ISR_OFF 0x00000030 |
| ADC Interrupt status register. | |
| #define | ADC_ISR (*((reg32_t *)(ADC_BASE + ADC_ISR_OFF))) |
| Interrupt status register. | |
| #define | ADC_EOC_MASK 0x000000FF |
| End of converison mask. | |
| #define | ADC_EOC0 0 |
| End of conversion channel 0. | |
| #define | ADC_EOC1 1 |
| End of conversion channel 1. | |
| #define | ADC_EOC2 2 |
| End of conversion channel 2. | |
| #define | ADC_EOC3 3 |
| End of conversion channel 3. | |
| #define | ADC_EOC4 4 |
| End of conversion channel 4. | |
| #define | ADC_EOC5 5 |
| End of conversion channel 5. | |
| #define | ADC_EOC6 6 |
| End of conversion channel 6. | |
| #define | ADC_EOC7 7 |
| End of conversion channel 7. | |
| #define | ADC_OVRE0 8 |
| Overrun error channel 0. | |
| #define | ADC_OVRE1 9 |
| Overrun error channel 1. | |
| #define | ADC_OVRE2 10 |
| Overrun error channel 2. | |
| #define | ADC_OVRE3 11 |
| Overrun error channel 3. | |
| #define | ADC_OVRE4 12 |
| Overrun error channel 4. | |
| #define | ADC_OVRE5 13 |
| Overrun error channel 5. | |
| #define | ADC_OVRE6 14 |
| Overrun error channel 6. | |
| #define | ADC_OVRE7 15 |
| Overrun error channel 7. | |
| #define | ADC_DRDY 24 |
| Data ready. | |
| #define | ADC_GOVRE 25 |
| General overrun error. | |
| #define | ADC_COMPE 26 |
| Comparition event interrupt mask. | |
| #define | ADC_ENDRX 27 |
| End of RX buffer. | |
| #define | ADC_RXBUFF 28 |
| Rx buffer full. | |
| #define | ADC_CR_OFF 0x00000000 |
| ADC control register. | |
| #define | ADC_CR (*((reg32_t *)(ADC_BASE + ADC_CR_OFF))) |
| Control register address. | |
| #define | ADC_SWRST 0 |
| Software reset. | |
| #define | ADC_START 1 |
| Start conversion. | |
| #define | ADC_MR_OFF 0x00000004 |
| ADC mode register. | |
| #define | ADC_MR (*((reg32_t *)(ADC_BASE + ADC_MR_OFF))) |
| Mode register address. | |
| #define | ADC_TRGEN 0 |
| Trigger enable. | |
| #define | ADC_TRGSEL_TIOA0 0x00000000 |
| TIOA output of the timer counter channel 0. | |
| #define | ADC_TRGSEL_TIOA1 0x00000002 |
| TIOA output of the timer counter channel 1. | |
| #define | ADC_TRGSEL_TIOA2 0x00000004 |
| TIOA output of the timer counter channel 2. | |
| #define | ADC_TRGSEL_PWM0 0x0000000A |
| PWM Event Line 0. | |
| #define | ADC_TRGSEL_PWM1 0x0000000C |
| PWM Event Line 1. | |
| #define | ADC_LOWRES 4 |
| Resolution 0: 12-bit, 1: 10-bit. | |
| #define | ADC_SLEEP 5 |
| Sleep mode. | |
| #define | ADC_FREERUN 7 |
| Freerun. | |
| #define | ADC_PRESCALER_MASK 0x0000FF00 |
| Prescaler rate selection. | |
| #define | ADC_PRESCALER_SHIFT 8 |
| Prescale rate selection shift. | |
| #define | ADC_STARTUP_MASK 0x000F0000 |
| Start up timer. | |
| #define | ADC_STARTUP_SHIFT 16 |
| Start up timer shift. | |
| #define | ADC_SUT0 0 |
| Start up timer. | |
| #define | ADC_SUT8 1 |
| 8 period of ADCClock. | |
| #define | ADC_SUT16 2 |
| 16 period of ADCClock. | |
| #define | ADC_SUT24 3 |
| 24 period of ADCClock. | |
| #define | ADC_SUT64 4 |
| 64 period of ADCClock. | |
| #define | ADC_SUT80 5 |
| 80 period of ADCClock. | |
| #define | ADC_SUT96 6 |
| 96 period of ADCClock. | |
| #define | ADC_SUT112 7 |
| 112 period of ADCClock. | |
| #define | ADC_SUT512 8 |
| 512 period of ADCClock. | |
| #define | ADC_SUT576 9 |
| 576 period of ADCClock. | |
| #define | ADC_SUT640 10 |
| 640 period of ADCClock. | |
| #define | ADC_SUT704 11 |
| 704 period of ADCClock. | |
| #define | ADC_SUT768 12 |
| 768 period of ADCClock. | |
| #define | ADC_SUT832 13 |
| 832 period of ADCClock. | |
| #define | ADC_SUT896 14 |
| 896 period of ADCClock. | |
| #define | ADC_SUT960 15 |
| 896 period of ADCClock. | |
| #define | ADC_LCDR_OFF 0x00000020 |
| ADC last convert data register. | |
| #define | ADC_LCDR (*((reg32_t *)(ADC_BASE + ADC_LCDR_OFF))) |
| Last converted RAW data register. | |
| #define | ADC_LDATA (ADC_LCDR & 0xFFF) |
| Last data converted register. | |
| #define | ADC_CHNB ((ADC_LCDR & 0xF000) >> 12) |
| Channel number. | |
| #define | ADC_CDR_OFF 0x00000050 |
| ADC Channel data register. | |
| #define | ADC_CDR (*((reg32_t *)(ADC_BASE + ADC_CDR_OFF))) |
| Channel data register. | |
| #define | ADC_ACR_OFF 0x00000094 |
| ADC Analog Control register. | |
| #define | ADC_ACR (*((reg32_t *)(ADC_BASE + ADC_ACR_OFF))) |
| Analog control register. | |
| #define | ADC_TSON 4 |
| Temperature Sensor On. | |
| #define | ADC_TEMPERATURE_CH 15 |
| Channel where is the internal sensor temperature. | |
Detailed Description
SAM3 Analog to Digital Converter.
Definition in file sam3_adc.h.
Define Documentation
| #define ADC_ACR_OFF 0x00000094 |
ADC Analog Control register.
Analog control register offeset.
Definition at line 248 of file sam3_adc.h.
| #define ADC_BASE 0x400C0000 |
ADC registers base.
Definition at line 46 of file sam3_adc.h.
| #define ADC_CDR_OFF 0x00000050 |
ADC Channel data register.
Channel data register offeset.
Definition at line 239 of file sam3_adc.h.
| #define ADC_CHDR_OFF 0x00000014 |
ADC channel disable register.
Channel disable register offeset.
Definition at line 148 of file sam3_adc.h.
| #define ADC_CHER_OFF 0x00000010 |
ADC channel enable register.
Channel enable register offeset.
Definition at line 142 of file sam3_adc.h.
| #define ADC_CHSR_OFF 0x00000018 |
ADC channel status register.
Channel status register offeset.
Definition at line 154 of file sam3_adc.h.
| #define ADC_CR_OFF 0x00000000 |
| #define ADC_IDR_OFF 0x00000028 |
ADC Interrupt disable register.
Interrupt disable register offeset.
Definition at line 184 of file sam3_adc.h.
| #define ADC_IER_OFF 0x00000024 |
ADC Interrupt enable register.
Interrupt enable register offeset.
Definition at line 178 of file sam3_adc.h.
| #define ADC_IMR_OFF 0x0000002C |
ADC Interrupt mask register.
Interrupt mask register offeset.
Definition at line 190 of file sam3_adc.h.
| #define ADC_ISR_OFF 0x00000030 |
ADC Interrupt status register.
Interrupt status register offeset.
Definition at line 196 of file sam3_adc.h.
| #define ADC_LCDR_OFF 0x00000020 |
ADC last convert data register.
Last converted data register offeset.
Definition at line 228 of file sam3_adc.h.
| #define ADC_MR_OFF 0x00000004 |
| #define ADC_PRESCALER_MASK 0x0000FF00 |
Prescaler rate selection.
ADCClock = MCK / ((ADC_PRESCALER_VALUE + 1) * 2) Prescaler rate selection mask.
Definition at line 80 of file sam3_adc.h.
| #define ADC_SETTLING_MASK 0x00300000 |
| #define ADC_SR_OFF 0x0000001C |
| #define ADC_STARTUP_MASK 0x000F0000 |
| #define ADC_SUT0 0 |
| #define ADC_TRACKTIM_MASK 0x0F000000 |
Tracking Time.
Tracking Time = (TRACKTIM + 1) * ADCClock periods. Tracking Time mask.
Definition at line 127 of file sam3_adc.h.
| #define ADC_TRANSFER_MASK 0x30000000 |
Transfer Period.
Transfer Period = (TRANSFER * 2 + 3) ADCClock periods. Transfer Period mask.
Definition at line 134 of file sam3_adc.h.
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