sam3_dacc.h File Reference
#include <io/cm3.h>Go to the source code of this file.
Defines | |
| #define | DACC_BASE 0x400C8000 |
| DACC registers base. | |
| #define | DACC_MR_STARTUP_0 0 |
| 0 periods of DACClock | |
| #define | DACC_MR_STARTUP_8 1 |
| 8 periods of DACClock | |
| #define | DACC_MR_STARTUP_16 2 |
| 16 periods of of DACClock | |
| #define | DACC_MR_STARTUP_24 3 |
| 24 periods of of DACClock | |
| #define | DACC_MR_STARTUP_64 4 |
| 64 periods of of DACClock | |
| #define | DACC_MR_STARTUP_80 5 |
| 70 periods of of DACClock | |
| #define | DACC_MR_STARTUP_96 6 |
| 96 periods of of DACClock | |
| #define | DACC_MR_STARTUP_112 7 |
| 112 periods of of DACClock | |
| #define | DACC_MR_STARTUP_512 8 |
| 512 periods of DACClock | |
| #define | DACC_MR_STARTUP_576 9 |
| 576 periods of DACClock | |
| #define | DACC_MR_STARTUP_640 10 |
| 640 periods of DACClock | |
| #define | DACC_MR_STARTUP_704 11 |
| 704 periods of DACClock | |
| #define | DACC_MR_STARTUP_768 12 |
| 768 periods of DACClock | |
| #define | DACC_MR_STARTUP_832 13 |
| 832 periods of DACClock | |
| #define | DACC_MR_STARTUP_896 14 |
| 896 periods of DACClock | |
| #define | DACC_MR_STARTUP_960 15 |
| 960 periods of DACClock | |
| #define | DACC_MR_STARTUP_1024 16 |
| 1024 periods of DACClock | |
| #define | DACC_MR_STARTUP_1088 17 |
| 1088 periods of DACClock | |
| #define | DACC_MR_STARTUP_1152 18 |
| 1152 periods of DACClock | |
| #define | DACC_MR_STARTUP_1216 19 |
| 1216 periods of DACClock | |
| #define | DACC_MR_STARTUP_1280 20 |
| 1280 periods of DACClock | |
| #define | DACC_MR_STARTUP_1344 21 |
| 1344 periods of DACClock | |
| #define | DACC_MR_STARTUP_1408 22 |
| 1408 periods of DACClock | |
| #define | DACC_MR_STARTUP_1472 23 |
| 1472 periods of DACClock | |
| #define | DACC_MR_STARTUP_1536 24 |
| 1536 periods of DACClock | |
| #define | DACC_MR_STARTUP_1600 25 |
| 1600 periods of DACClock | |
| #define | DACC_MR_STARTUP_1664 26 |
| 1664 periods of DACClock | |
| #define | DACC_MR_STARTUP_1728 27 |
| 1728 periods of DACClock | |
| #define | DACC_MR_STARTUP_1792 28 |
| 1792 periods of DACClock | |
| #define | DACC_MR_STARTUP_1856 29 |
| 1856 periods of DACClock | |
| #define | DACC_MR_STARTUP_1920 30 |
| 1920 periods of DACClock | |
| #define | DACC_MR_STARTUP_1984 31 |
| 1984 periods of DACClock | |
| #define | DACC_CHER_OFF 0x00000010 |
| DACC channel enable register. | |
| #define | DACC_CHER (*((reg32_t*) (DACC_BASE + DACC_CHER_OFF))) |
| Channel enable register address. | |
| #define | DACC_CHDR_OFF 0x00000014 |
| DACC channel disable register. | |
| #define | DACC_CHDR (*((reg32_t*) (DACC_BASE + DACC_CHDR_OFF))) |
| Channel disable register address. | |
| #define | DACC_CHSR_OFF 0x00000018 |
| DACC channel status register. | |
| #define | DACC_CHSR (*((reg32_t*) (DACC_BASE + DACC_CHSR_OFF))) |
| Channel status register address. | |
| #define | DACC_CH0 0 |
| Channel 0. | |
| #define | DACC_CH1 1 |
| Channel 1. | |
| #define | DACC_CDR_OFF 0x00000020 |
| DACC Conversion data register. | |
| #define | DACC_CDR (*((reg32_t*) (DACC_BASE + DACC_CDR_OFF))) |
| Conversion data register address. | |
| #define | DACC_IER_OFF 0x00000024 |
| DACC Interrupt enable register. | |
| #define | DACC_IER (*((reg32_t*) (DACC_BASE + DACC_IER_OFF))) |
| Interrupt enable register address. | |
| #define | DACC_IDR_OFF 0x00000028 |
| DACC Interrupt disable register. | |
| #define | DACC_IDR (*((reg32_t*) (DACC_BASE + DACC_IDR_OFF))) |
| Interrupt disable register address. | |
| #define | DACC_IMR_OFF 0x0000002C |
| DACC Interrupt disable register. | |
| #define | DACC_IMR (*((reg32_t*) (DACC_BASE + DACC_IMR_OFF))) |
| Interrupt mask register address. | |
| #define | DACC_ISR_OFF 0x00000030 |
| DACC Interrupt status register. | |
| #define | DACC_ISR (*((reg32_t*) (DACC_BASE + DACC_ISR_OFF))) |
| Interrupt status register address. | |
| #define | DACC_TXRDY 0 |
| Transmit ready interrupt. | |
| #define | DACC_EOC 1 |
| End of conversion interrupt. | |
| #define | DACC_ENDTX 2 |
| End of DMA Interrupt Flag. | |
| #define | DACC_TXBUFE 3 |
| Transmit buffer empty interrupt. | |
| #define | DACC_RPR (*((reg32_t*) (DACC_BASE + PERIPH_RPR_OFF))) |
| DMA controller for DACC DACC PDC register. | |
| #define | DACC_RCR (*((reg32_t*) (DACC_BASE + PERIPH_RCR_OFF))) |
| Receive Counter Register. | |
| #define | DACC_TPR (*((reg32_t*) (DACC_BASE + PERIPH_TPR_OFF))) |
| Transmit Pointer Register. | |
| #define | DACC_TCR (*((reg32_t*) (DACC_BASE + PERIPH_TCR_OFF))) |
| Transmit Counter Register. | |
| #define | DACC_RNPR (*((reg32_t*) (DACC_BASE + PERIPH_RNPR_OFF))) |
| Receive Next Pointer Register. | |
| #define | DACC_RNCR (*((reg32_t*) (DACC_BASE + PERIPH_RNCR_OFF))) |
| Receive Next Counter Register. | |
| #define | DACC_TNPR (*((reg32_t*) (DACC_BASE + PERIPH_TNPR_OFF))) |
| Transmit Next Pointer Register. | |
| #define | DACC_TNCR (*((reg32_t*) (DACC_BASE + PERIPH_TNCR_OFF))) |
| Transmit Next Counter Register. | |
| #define | DACC_PTCR (*((reg32_t*) (DACC_BASE + PERIPH_PTCR_OFF))) |
| Transfer Control Register. | |
| #define | DACC_PTSR (*((reg32_t*) (DACC_BASE + PERIPH_PTSR_OFF))) |
| Transfer Status Register. | |
| #define | DACC_PTCR_RXTEN 0 |
| DACC_PTCR Receiver Transfer Enable. | |
| #define | DACC_PTCR_RXTDIS 1 |
| DACC_PTCR Receiver Transfer Disable. | |
| #define | DACC_PTCR_TXTEN 8 |
| DACC_PTCR Transmitter Transfer Enable. | |
| #define | DACC_PTCR_TXTDIS 9 |
| DACC_PTCR Transmitter Transfer Disable. | |
| #define | DACC_PTSR_RXTEN 0 |
| DACC_PTSR Receiver Transfer Enable. | |
| #define | DACC_PTSR_TXTEN 8 |
| DACC_PTSR Transmitter Transfer Enable. | |
| #define | DACC_CR_OFF 0x00000000 |
| DACC control register. | |
| #define | DACC_CR (*((reg32_t*)(DACC_BASE + DACC_CR_OFF))) |
| Control register address. | |
| #define | DACC_SWRST 0 |
| Software reset. | |
| #define | DACC_MR_OFF 0x00000004 |
| DACC mode register. | |
| #define | DACC_MR (*((reg32_t*) (DACC_BASE + DACC_MR_OFF))) |
| Mode register address. | |
| #define | DACC_TRGEN 0 |
| Trigger enable. | |
| #define | DACC_TRGSEL_MASK 0x14 |
| Trigger selection mask. | |
| #define | DACC_TRGSEL_SHIFT 1 |
| Trigger selection shift. | |
| #define | DACC_WORD 4 |
| Word transfer. | |
| #define | DACC_SLEEP 5 |
| Sleep mode.Fast Wake up Mode. | |
| #define | DACC_FASTWKUP 6 |
| Fast Wake up Mode. | |
| #define | DACC_REFRESH_MASK 0xFF00 |
| Refresh Period mask. | |
| #define | DACC_REFRESH_SHIFT 8 |
| Refresh Period shift. | |
| #define | DACC_USER_SEL_MASK 0x30000 |
| User Channel Selection mask. | |
| #define | DACC_USER_SEL_SHIFT 16 |
| User Channel Selection shift. | |
| #define | DACC_TAG 20 |
| Tag selection mode. | |
| #define | DACC_MAXS 21 |
| Max speed mode. | |
| #define | DACC_STARTUP_MASK 0x3F000000 |
| Startup time selection. | |
| #define | DACC_STARTUP_SHIFT 24 |
| Startup time selsection shift. | |
| #define | DACC_TRGSEL_TIO_CH0 1 |
| Trigger selection. | |
| #define | DACC_TRGSEL_TIO_CH1 2 |
| DACC mode register. | |
| #define | DACC_TRGSEL_TIO_CH2 3 |
| DACC mode register. | |
| #define | DACC_TRGSEL_PWM0 4 |
| DACC mode register. | |
| #define | DACC_TRGSEL_PWM1 5 |
| DACC mode register. | |
Detailed Description
SAM3 Digital to Analog to Converter.
Definition in file sam3_dacc.h.
Define Documentation
| #define DACC_BASE 0x400C8000 |
DACC registers base.
Definition at line 47 of file sam3_dacc.h.
| #define DACC_CDR_OFF 0x00000020 |
DACC Conversion data register.
Conversion data register offeset.
Definition at line 151 of file sam3_dacc.h.
| #define DACC_CHDR_OFF 0x00000014 |
DACC channel disable register.
Channel disable register offeset.
Definition at line 135 of file sam3_dacc.h.
| #define DACC_CHER_OFF 0x00000010 |
DACC channel enable register.
Channel enable register offeset.
Definition at line 129 of file sam3_dacc.h.
| #define DACC_CHSR_OFF 0x00000018 |
DACC channel status register.
Channel status register offeset.
Definition at line 141 of file sam3_dacc.h.
| #define DACC_CR_OFF 0x00000000 |
| #define DACC_IDR_OFF 0x00000028 |
DACC Interrupt disable register.
Interrupt disable register offeset.
Definition at line 164 of file sam3_dacc.h.
| #define DACC_IER_OFF 0x00000024 |
DACC Interrupt enable register.
Interrupt enable register offeset.
Definition at line 158 of file sam3_dacc.h.
| #define DACC_IMR_OFF 0x0000002C |
DACC Interrupt disable register.
Interrupt mask register offeset.
Definition at line 170 of file sam3_dacc.h.
| #define DACC_ISR_OFF 0x00000030 |
DACC Interrupt status register.
Interrupt disable status offeset.
Definition at line 176 of file sam3_dacc.h.
| #define DACC_MR_OFF 0x00000004 |
| #define DACC_RPR (*((reg32_t*) (DACC_BASE + PERIPH_RPR_OFF))) |
DMA controller for DACC DACC PDC register.
Receive Pointer Register.
Definition at line 189 of file sam3_dacc.h.
| #define DACC_TRGSEL_PWM0 4 |
| #define DACC_TRGSEL_PWM1 5 |
| #define DACC_TRGSEL_TIO_CH1 2 |
| #define DACC_TRGSEL_TIO_CH2 3 |
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