sam3_flash.h

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00001 
00036 #ifndef SAM3_FLASH_H
00037 #define SAM3_FLASH_H
00038 
00042 /*\{*/
00043 #define EEFC0_BASE  0x400E0A00
00044 #ifdef CPU_CM3_SAM3X
00045     #define EEFC1_BASE  0x400E0C00
00046 #endif
00047 /*\}*/
00048 
00049 
00053 /*\{*/
00054 #define EEFC_FMR_OFF  0x0   ///< Flash Mode Register
00055 #define EEFC_FCR_OFF  0x4   ///< Flash Command Register
00056 #define EEFC_FSR_OFF  0x8   ///< Flash Status Register
00057 #define EEFC_FRR_OFF  0xC   ///< Flash Result Register
00058 /*\}*/
00059 
00063 /*\{*/
00064 #define EEFC0_FMR  (*((reg32_t *)(EEFC0_BASE + EEFC_FMR_OFF)))  ///< Flash Mode Register
00065 #define EEFC0_FCR  (*((reg32_t *)(EEFC0_BASE + EEFC_FCR_OFF)))  ///< Flash Command Register
00066 #define EEFC0_FSR  (*((reg32_t *)(EEFC0_BASE + EEFC_FSR_OFF)))  ///< Flash Status Register
00067 #define EEFC0_FRR  (*((reg32_t *)(EEFC0_BASE + EEFC_FRR_OFF)))  ///< Flash Result Register
00068 
00069 #ifdef CPU_CM3_SAM3X
00070     #define EEFC1_FMR  (*((reg32_t *)(EEFC1_BASE + EEFC_FMR_OFF)))  ///< Flash Mode Register
00071     #define EEFC1_FCR  (*((reg32_t *)(EEFC1_BASE + EEFC_FCR_OFF)))  ///< Flash Command Register
00072     #define EEFC1_FSR  (*((reg32_t *)(EEFC1_BASE + EEFC_FSR_OFF)))  ///< Flash Status Register
00073     #define EEFC1_FRR  (*((reg32_t *)(EEFC1_BASE + EEFC_FRR_OFF)))  ///< Flash Result Register
00074 #endif
00075 /*\}*/
00076 
00077 
00078 
00082 /*\{*/
00083 #define EEFC_FMR_FRDY        0                       ///< Ready Interrupt Enable
00084 #define EEFC_FMR_FWS_SHIFT   8
00085 #define EEFC_FMR_FWS_MASK    (0xf << EEFC_FMR_FWS_SHIFT) ///< Flash Wait State
00086 #define EEFC_FMR_FWS(value)  (EEFC_FMR_FWS_MASK & ((value) << EEFC_FMR_FWS_SHIFT))
00087 #define EEFC_FMR_FAM         24                      ///< Flash Access Mode
00088 /*\}*/
00089 
00093 /*\{*/
00094 #define EEFC_FCR_FCMD_MASK    0xff                        ///< Flash Command
00095 #define EEFC_FCR_FCMD(value)  (EEFC_FCR_FCMD_MASK & (value))
00096 #define EEFC_FCR_FARG_SHIFT   8
00097 #define EEFC_FCR_FARG_MASK    (0xffff << EEFC_FCR_FARG_SHIFT) ///< Flash Command Argument
00098 #define EEFC_FCR_FARG(value)  (EEFC_FCR_FARG_MASK & ((value) << EEFC_FCR_FARG_SHIFT))
00099 #define EEFC_FCR_FKEY_SHIFT   24
00100 #define EEFC_FCR_FKEY_MASK    (0xff << EEFC_FCR_FKEY_SHIFT)   ///< Flash Writing Protection Key
00101 #define EEFC_FCR_FKEY(value)  (EEFC_FCR_FKEY_MASK & ((value) << EEFC_FCR_FKEY_SHIFT))
00102 /*\}*/
00103 
00107 /*\{*/
00108 #define EEFC_FSR_FRDY       0  ///< Flash Ready Status
00109 #define EEFC_FSR_FCMDE      1  ///< Flash Command Error Status
00110 #define EEFC_FSR_FLOCKE     2  ///< Flash Lock Error Status
00111 /*\}*/
00112 
00113 #endif /* SAM3_FLASH_H */