sam3_tc.h

Go to the documentation of this file.
00001 
00041 #ifndef SAM3_TC_H
00042 #define SAM3_TC_H
00043 
00045 #define TC0_BASE        0x40080000  ///< TC0 Base Address.
00046 #define TC1_BASE        0x40084000  ///< TC1 Base Address.
00047 #define TC2_BASE        0x40088000  ///< TC2 Base Address.
00048 
00052 #define TC0_CCR0_OFF              0x00  ///< TC0 Channel Control Register (channel = 0).
00053 #define TC0_CCR0              (*((reg32_t*)(TC0_BASE + TC0_CCR0_OFF)))     ///< TC0 Channel Control Register (channel = 0).
00054 
00055 #define TC0_CMR0_OFF              0x04  ///< TC0 Channel Mode Register (channel = 0).
00056 #define TC0_CMR0              (*((reg32_t*)(TC0_BASE + TC0_CMR0_OFF))) ///< TC0 Channel Mode Register (channel = 0).
00057 
00058 #define TC_CMR_CPCTRG              14   ///< RC Compare Trigger Enable
00059 #define TC_CMR_WAVE                15   ///< Waveform mode is enabled
00060 
00061 #define TC_CMR_ACPA_SET          0x10000 ///< RA Compare Effect: set
00062 #define TC_CMR_ACPA_CLEAR        0x20000 ///< RA Compare Effect: clear
00063 #define TC_CMR_ACPA_TOGGLE       0x30000 ///< RA Compare Effect: toggle
00064 
00065 #define TC_CMR_ACPC_SET          0x40000 ///< RC Compare Effect: set
00066 #define TC_CMR_ACPC_CLEAR        0x80000 ///< RC Compare Effect: clear
00067 #define TC_CMR_ACPC_TOGGLE       0xC0000 ///< RC Compare Effect: toggle
00068 
00069 #define TC_CCR_CLKEN                 0 ///< Counter Clock Enable Command
00070 #define TC_CCR_CLKDIS                1 ///< Counter Clock Disable Command
00071 #define TC_CCR_SWTRG                 2 ///< Software Trigger Command
00072 
00073 #define TC_TIMER_CLOCK1              0 ///< Select timer clock TCLK1
00074 #define TC_TIMER_CLOCK2              1 ///< Select timer clock TCLK2
00075 
00076 #define TC0_SMMR0_OFF             0x08  ///< TC0 Stepper Motor Mode Register (channel = 0).
00077 #define TC0_SMMR0             (*((reg32_t*)(TC0_BASE + TC0_SMMR0_OFF)))  ///< TC0 Stepper Motor Mode Register (channel = 0).
00078 
00079 #define TC0_CV0_OFF               0x10  ///< TC0 Conter Vale (channel = 0).
00080 #define TC0_CV0               (*((reg32_t*)(TC0_BASE + TC0_CV0_OFF)))  ///< TC0 Conter Vale (channel = 0).
00081 
00082 #define TC0_RA0_OFF               0x14  ///< TC0 Register A (channel = 0).
00083 #define TC0_RA0               (*((reg32_t*)(TC0_BASE + TC0_RA0_OFF)))  ///< TC0 Register A (channel = 0).
00084 
00085 #define TC0_RB0_OFF               0x18  ///< TC0 Register B (channel = 0).
00086 #define TC0_RB0               (*((reg32_t*)(TC0_BASE + TC0_RB0_OFF)))  ///< TC0 Register B (channel = 0).
00087 
00088 #define TC0_RC0_OFF               0x1C  ///< TC0 Register C (channel = 0).
00089 #define TC0_RC0               (*((reg32_t*)(TC0_BASE + TC0_RC0_OFF)))  ///< TC0 Register C (channel = 0).
00090 
00091 #define TC0_SR0_OFF               0x20  ///< TC0 Stats Register (channel = 0).
00092 #define TC0_SR0               (*((reg32_t*)(TC0_BASE + TC0_SR0_OFF)))  ///< TC0 Stats Register (channel = 0).
00093 
00094 #define TC0_IER0_OFF              0x24  ///< TC0 Interrpt Enable Register (channel = 0).
00095 #define TC0_IER0              (*((reg32_t*)(TC0_BASE + TC0_IER0_OFF)))  ///< TC0 Interrpt Enable Register (channel = 0).
00096 
00097 #define TC0_IDR0_OFF              0x28  ///< TC0 Interrpt Disable Register (channel = 0).
00098 #define TC0_IDR0              (*((reg32_t*)(TC0_BASE + TC0_IDR0_OFF)))  ///< TC0 Interrpt Disable Register (channel = 0).
00099 
00100 #define TC0_IMR0_OFF              0x2C  ///< TC0 Interrpt Mask Register (channel = 0).
00101 #define TC0_IMR0              (*((reg32_t*)(TC0_BASE + TC0_IMR0_OFF)))  ///< TC0 Interrpt Mask Register (channel = 0).
00102 
00103 #define TC0_CCR1_OFF              0x40  ///< TC0 Channel Control Register (channel = 1).
00104 #define TC0_CCR1              (*((reg32_t*)(TC0_BASE + TC0_CCR1_OFF)))  ///< TC0 Channel Control Register (channel = 1).
00105 
00106 #define TC0_CMR1_OFF              0x44  ///< TC0 Channel Mode Register (channel = 1).
00107 #define TC0_CMR1              (*((reg32_t*)(TC0_BASE + TC0_CMR1_OFF)))  ///< TC0 Channel Mode Register (channel = 1).
00108 
00109 #define TC0_SMMR1_OFF             0x48  ///< TC0 Stepper Motor Mode Register (channel = 1).
00110 #define TC0_SMMR1             (*((reg32_t*)(TC0_BASE + TC0_SMMR1_OFF)))  ///< TC0 Stepper Motor Mode Register (channel = 1).
00111 
00112 #define TC0_CV1_OFF               0x50  ///< TC0 Conter Vale (channel = 1).
00113 #define TC0_CV1               (*((reg32_t*)(TC0_BASE + TC0_CV1_OFF)))  ///< TC0 Conter Vale (channel = 1).
00114 
00115 #define TC0_RA1_OFF               0x54  ///< TC0 Register A (channel = 1).
00116 #define TC0_RA1               (*((reg32_t*)(TC0_BASE + TC0_RA1_OFF)))  ///< TC0 Register A (channel = 1).
00117 
00118 #define TC0_RB1_OFF               0x58  ///< TC0 Register B (channel = 1).
00119 #define TC0_RB1               (*((reg32_t*)(TC0_BASE + TC0_RB1_OFF)))  ///< TC0 Register B (channel = 1).
00120 
00121 #define TC0_RC1_OFF               0x5C  ///< TC0 Register C (channel = 1).
00122 #define TC0_RC1               (*((reg32_t*)(TC0_BASE + TC0_RC1_OFF)))  ///< TC0 Register C (channel = 1).
00123 
00124 #define TC0_SR1_OFF               0x60  ///< TC0 Stats Register (channel = 1).
00125 #define TC0_SR1               (*((reg32_t*)(TC0_BASE + TC0_SR1_OFF)))  ///< TC0 Stats Register (channel = 1).
00126 
00127 #define TC0_IER1_OFF              0x64  ///< TC0 Interrpt Enable Register (channel = 1).
00128 #define TC0_IER1              (*((reg32_t*)(TC0_BASE + TC0_IER1_OFF)))  ///< TC0 Interrpt Enable Register (channel = 1).
00129 
00130 #define TC0_IDR1_OFF              0x68  ///< TC0 Interrpt Disable Register (channel = 1).
00131 #define TC0_IDR1              (*((reg32_t*)(TC0_BASE + TC0_IDR1_OFF)))  ///< TC0 Interrpt Disable Register (channel = 1).
00132 
00133 #define TC0_IMR1_OFF              0x6C  ///< TC0 Interrpt Mask Register (channel = 1).
00134 #define TC0_IMR1              (*((reg32_t*)(TC0_BASE + TC0_IMR1_OFF)))  ///< TC0 Interrpt Mask Register (channel = 1).
00135 
00136 #define TC0_CCR2_OFF              0x80  ///< TC0 Channel Control Register (channel = 2).
00137 #define TC0_CCR2              (*((reg32_t*)(TC0_BASE + TC0_CCR2_OFF)))  ///< TC0 Channel Control Register (channel = 2).
00138 
00139 #define TC0_CMR2_OFF              0x84  ///< TC0 Channel Mode Register (channel = 2).
00140 #define TC0_CMR2              (*((reg32_t*)(TC0_BASE + TC0_CMR2_OFF)))  ///< TC0 Channel Mode Register (channel = 2).
00141 
00142 #define TC0_SMMR2_OFF             0x88  ///< TC0 Stepper Motor Mode Register (channel = 2).
00143 #define TC0_SMMR2             (*((reg32_t*)(TC0_BASE + TC0_SMMR2_OFF)))  ///< TC0 Stepper Motor Mode Register (channel = 2).
00144 
00145 #define TC0_CV2_OFF               0x90  ///< TC0 Conter Vale (channel = 2).
00146 #define TC0_CV2               (*((reg32_t*)(TC0_BASE + TC0_CV2_OFF)))  ///< TC0 Conter Vale (channel = 2).
00147 
00148 #define TC0_RA2_OFF               0x94  ///< TC0 Register A (channel = 2).
00149 #define TC0_RA2               (*((reg32_t*)(TC0_BASE + TC0_RA2_OFF)))  ///< TC0 Register A (channel = 2).
00150 
00151 #define TC0_RB2_OFF               0x98  ///< TC0 Register B (channel = 2).
00152 #define TC0_RB2               (*((reg32_t*)(TC0_BASE + TC0_RB2_OFF)))  ///< TC0 Register B (channel = 2).
00153 
00154 #define TC0_RC2_OFF               0x9C  ///< TC0 Register C (channel = 2).
00155 #define TC0_RC2               (*((reg32_t*)(TC0_BASE + TC0_RC2_OFF)))  ///< TC0 Register C (channel = 2).
00156 
00157 #define TC0_SR2_OFF               0xA0  ///< TC0 Stats Register (channel = 2).
00158 #define TC0_SR2               (*((reg32_t*)(TC0_BASE + TC0_SR2_OFF)))  ///< TC0 Stats Register (channel = 2).
00159 
00160 #define TC0_IER2_OFF              0xA4  ///< TC0 Interrpt Enable Register (channel = 2).
00161 #define TC0_IER2              (*((reg32_t*)(TC0_BASE + TC0_IER2_OFF)))  ///< TC0 Interrpt Enable Register (channel = 2).
00162 
00163 #define TC0_IDR2_OFF              0xA8  ///< TC0 Interrpt Disable Register (channel = 2).
00164 #define TC0_IDR2              (*((reg32_t*)(TC0_BASE + TC0_IDR2_OFF)))  ///< TC0 Interrpt Disable Register (channel = 2).
00165 
00166 #define TC0_IMR2_OFF              0xAC  ///< TC0 Interrpt Mask Register (channel = 2).
00167 #define TC0_IMR2              (*((reg32_t*)(TC0_BASE + TC0_IMR2_OFF)))  ///< TC0 Interrpt Mask Register (channel = 2).
00168 
00169 #define TC0_BCR_OFF               0xC0  ///< TC0 Block Control Register.
00170 #define TC0_BCR               (*((reg32_t*)(TC0_BASE + TC0_BCR_OFF)))  ///< TC0 Block Control Register.
00171 
00172 #define TC0_BMR_OFF               0xC4  ///< TC0 Block Mode Register.
00173 #define TC0_BMR               (*((reg32_t*)(TC0_BASE + TC0_BMR_OFF)))  ///< TC0 Block Mode Register.
00174 
00175 #define TC0_QIER_OFF              0xC8  ///< TC0 QDEC Interrpt Enable Register.
00176 #define TC0_QIER              (*((reg32_t*)(TC0_BASE + TC0_QIER_OFF)))  ///< TC0 QDEC Interrpt Enable Register.
00177 
00178 #define TC0_QIDR_OFF              0xCC  ///< TC0 QDEC Interrpt Disable Register.
00179 #define TC0_QIDR              (*((reg32_t*)(TC0_BASE + TC0_QIDR_OFF)))  ///< TC0 QDEC Interrpt Disable Register.
00180 
00181 #define TC0_QIMR_OFF              0xD0  ///< TC0 QDEC Interrpt Mask Register.
00182 #define TC0_QIMR              (*((reg32_t*)(TC0_BASE + TC0_QIMR_OFF)))  ///< TC0 QDEC Interrpt Mask Register.
00183 
00184 #define TC0_QISR_OFF              0xD4  ///< TC0 QDEC Interrpt Stats Register.
00185 #define TC0_QISR              (*((reg32_t*)(TC0_BASE + TC0_QISR_OFF)))  ///< TC0 QDEC Interrpt Stats Register.
00186 
00187 #define TC0_FMR_OFF               0xD8  ///< TC0 Falt Mode Register.
00188 #define TC0_FMR               (*((reg32_t*)(TC0_BASE + TC0_FMR_OFF)))  ///< TC0 Falt Mode Register.
00189 
00190 #define TC0_WPMR_OFF              0xE4  ///< TC0 Write Protect Mode Register.
00191 #define TC0_WPMR              (*((reg32_t*)(TC0_BASE + TC0_WPMR_OFF)))  ///< TC0 Write Protect Mode Register.
00192 
00193 #endif /* SAM3_TC_H */