sam3_wdt.h

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/*
 * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
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#ifndef SAM3_WDT_H
#define SAM3_WDT_H

#if CPU_CM3_SAM3N
    #define WDT_BASE  0x400E1450
#elif CPU_CM3_SAM3X
    #define WDT_BASE  0x400E1A50
#endif

/*\{*/
#define WDT_CR_OFF          0x00000000  ///< Watchdog control register offset.
#define WDT_CR              (*((reg32_t *)(WDT_BASE + WDT_CR_OFF))) ///< Watchdog control register address.
#define WDT_WDRSTT          0           ///< Watchdog restart.
#define WDT_KEY             0xA5000000  ///< Watchdog password.
/*\}*/

/*\{*/
#define WDT_MR_OFF          0x00000004  ///< Mode register offset.
#define WDT_MR              (*((reg32_t *)(WDT_BASE + WDT_MR_OFF))) ///< Mode register address.
#define WDT_WDV_MASK        0x00000FFF  ///< Counter value mask.
#define WDT_WDV_SHIFT       0           ///< Counter value LSB.
#define WDT_WDFIEN          12          ///< Fault interrupt enable.
#define WDT_WDRSTEN         13          ///< Reset enable.
#define WDT_WDRPROC         14          ///< Eset processor enable.
#define WDT_WDDIS           15          ///< Watchdog disable.
#define WDT_WDD_MASK        0x0FFF0000  ///< Delta value mask.
#define WDT_WDD_SHIFT       16          ///< Delta value LSB.
#define WDT_WDDBGHLT        28          ///< Watchdog debug halt.
#define WDT_WDIDLEHLT       29          ///< Watchdog idle halt.
/*\}*/

/*\{*/
#define WDT_SR_OFF          0x00000008  ///< Status register offset.
#define WDT_SR              (*((reg32_t *)(WDT_BASE + WDT_SR_OFF))) ///< Status register address.
#define WDT_WDUNF           0  ///< Watchdog underflow.
#define WDT_WDERR           1  ///< Watchdog error.
/*\}*/

#endif /* SAM3_WDT_H */